Abstract: A package-free bonding pad structure on a silicon chip that includes a plurality of metal pads on the upper surface of the silicon chip and a passivation layer covering the upper surface of the silicon chip. The passivation layer has a plurality of open cavities directly above the metal pad areas for exposing a portion of each metal pad. Diameter of the open cavity gets smaller on approaching the upper surface of the passivation layer and grows bigger in the neighborhood of the metal pad area.
Abstract: Methods and apparatuses are disclosed for determining one or more characteristics of a sub-image within an electronic image.In one embodiment, the present invention includes an alpha image generator and a characterizer. The alpha image generator provides an alpha image of the subject being characterized, separated from a background of the input image. In another embodiment, the alpha image generator also may provide a summed area table. The characterizer determines a characteristic of the subject from the alpha image.In another embodiment, a first characteristic of the subject is derived from the alpha image. The characterizer determines a second characteristic based upon the first characteristic. In yet another embodiment, the determination of the second characteristic is simplified by eliminating all the unlikely estimates of the second characteristic in the overall potential estimates of the second characteristic.
Abstract: A microwave dielectric composition superior in all dielectric constant, product of resonant frequency by quality coefficient and temperature-dependent coefficient of resonant frequency, can be prepared by mixing a main oxide formulation consisting of lead oxide, calcium oxide, zirconium oxide and tin oxide with manganous nitrate (Mn(NO.sub.3).sub.2.4H.sub.2 O), calcining the mixture at a temperature of about 1,000 to 1,200.degree. C., pulverizing and molding the mixture, and sintering the molded body at a temperature of about 1,200 to 1,550.degree. C. in an oxygen atmosphere. It is 100 or greater in dielectric constant, 4,000 or greater in the product of resonant frequency by quality coefficient and .+-.3 mmp/.degree. C. or less in temperature-dependent coefficient of resonant frequency.
Type:
Grant
Filed:
June 30, 1998
Date of Patent:
February 22, 2000
Assignee:
Korea Advanced Institute of Science and Technology
Abstract: A method of manufacturing embedded DRAM capable of integrating memory circuit regions and logic circuit regions together such that their top surfaces are at the same height, and hence able to maintain a high degree of planarity in integrated circuits. The method includes depositing a layer of refractory metal oxide over a high aspect ratio contact hole. Then, through the selective application of a hydrogen plasma treatment or hot hydrogen treatment, a portion of the deposited refractory metal oxide on the contact hole is transformed from non-conductive to conductive material, whereas the refractory metal oxide without a hydrogen plasma treatment or hot hydrogen treatment remains non-conductive. Therefore, a non-conductive refractory metal oxide layer can be used as a dielectric layer for a DRAM capacitor.