Patents Represented by Law Firm Hickman Stephens Coleman & Hughes
  • Patent number: 6038820
    Abstract: The present invention provides a fabric, consisting of multiple cables and multiple panels, for roofing applications. The cables are arranged in sets of three over the area to be covered, and the panels are suspended between the cable sets to complete the fabric. Specifically, each panel has four attachment points and is suspended between two adjacent cable sets such that it attaches to two of the three cables in each set on either side of it. More specifically, each panel attaches to the middle cable of the two sets on either side, and to the top cable in one set and the bottom cable in the other set. This particular arrangement creates overlapping rows of overlapping panels that viewed from one perspective resembles overlapping shingles on a conventional roof, however, when viewed from another perspective reveals that the individual panels are held apart by the cable sets to allow air and light to diffuse through.
    Type: Grant
    Filed: July 8, 1999
    Date of Patent: March 21, 2000
    Assignee: John Rainbolt
    Inventor: John Rainbolt
  • Patent number: 6031776
    Abstract: A sense amplifier circuit for a semiconductor memory device. The sense amplifier of this invention has four more NMOS transistors than a conventional amplifier. The gate terminals of two of the NMOS transistors are connected to a write enable line. The gate terminals of the other two NMOS transistors are connected to a first and a second node point, which are in turn connected to a bit line and a complementary bit line, respectively. Through a feedback circuit provided by these four additional NMOS transistors, two of the NMOS transistors are switched on during a write cycle to provide a ground connection so that voltage level of the sense amplifier is rapidly pulled down. Since the latching speed of the sense amplifier is increased, the operating speed of the memory is increased, as well. In addition, partial writing of data can be avoided.
    Type: Grant
    Filed: August 17, 1999
    Date of Patent: February 29, 2000
    Assignee: United Microelectronics Corp.
    Inventors: Juei-Lung Chen, Hsin-Pang Lu
  • Patent number: 6031293
    Abstract: A package-free bonding pad structure on a silicon chip that includes a plurality of metal pads on the upper surface of the silicon chip and a passivation layer covering the upper surface of the silicon chip. The passivation layer has a plurality of open cavities directly above the metal pad areas for exposing a portion of each metal pad. Diameter of the open cavity gets smaller on approaching the upper surface of the passivation layer and grows bigger in the neighborhood of the metal pad area.
    Type: Grant
    Filed: April 26, 1999
    Date of Patent: February 29, 2000
    Assignee: United Microelectronics Corporation
    Inventors: Min-Chih Hsuan, Fu-Tai Liou
  • Patent number: 6030878
    Abstract: A method of fabricating a capacitor includes formation of a first dielectric layer having a contact hole on a substrate. A conductive layer is formed over the substrate and is electrically coupled with a source/drain region through the contact hole. An isolation layer is formed on the conductive layer. The isolation layer and the conductive layer are patterned to form a patterned isolation layer and a raised region over the contact hole. A first spacer is formed on the sidewall of the patterned isolation layer and the raised region. The patterned isolation layer is removed. The first spacer is used as a mask to etch the conductive layer to form another two sidewalls. The first spacer is removed. Two spacers are formed on the two sidewalls and used as masks. The conductive layer is patterned again to form two raised regions concentrically in shape.
    Type: Grant
    Filed: November 25, 1998
    Date of Patent: February 29, 2000
    Assignee: United Microelectronics Corp.
    Inventors: Chia-Hung Kao, Hal Lee
  • Patent number: 6031934
    Abstract: Methods and apparatuses are disclosed for determining one or more characteristics of a sub-image within an electronic image.In one embodiment, the present invention includes an alpha image generator and a characterizer. The alpha image generator provides an alpha image of the subject being characterized, separated from a background of the input image. In another embodiment, the alpha image generator also may provide a summed area table. The characterizer determines a characteristic of the subject from the alpha image.In another embodiment, a first characteristic of the subject is derived from the alpha image. The characterizer determines a second characteristic based upon the first characteristic. In yet another embodiment, the determination of the second characteristic is simplified by eliminating all the unlikely estimates of the second characteristic in the overall potential estimates of the second characteristic.
    Type: Grant
    Filed: October 15, 1997
    Date of Patent: February 29, 2000
    Assignee: Electric Planet, Inc.
    Inventors: Subutai Ahmad, Kevin L. Hunter
  • Patent number: 6028021
    Abstract: A microwave dielectric composition superior in all dielectric constant, product of resonant frequency by quality coefficient and temperature-dependent coefficient of resonant frequency, can be prepared by mixing a main oxide formulation consisting of lead oxide, calcium oxide, zirconium oxide and tin oxide with manganous nitrate (Mn(NO.sub.3).sub.2.4H.sub.2 O), calcining the mixture at a temperature of about 1,000 to 1,200.degree. C., pulverizing and molding the mixture, and sintering the molded body at a temperature of about 1,200 to 1,550.degree. C. in an oxygen atmosphere. It is 100 or greater in dielectric constant, 4,000 or greater in the product of resonant frequency by quality coefficient and .+-.3 mmp/.degree. C. or less in temperature-dependent coefficient of resonant frequency.
    Type: Grant
    Filed: June 30, 1998
    Date of Patent: February 22, 2000
    Assignee: Korea Advanced Institute of Science and Technology
    Inventors: Ho Gi Kim, Yung Park, Tae Suk Chung
  • Patent number: 6017790
    Abstract: A method of manufacturing embedded DRAM capable of integrating memory circuit regions and logic circuit regions together such that their top surfaces are at the same height, and hence able to maintain a high degree of planarity in integrated circuits. The method includes depositing a layer of refractory metal oxide over a high aspect ratio contact hole. Then, through the selective application of a hydrogen plasma treatment or hot hydrogen treatment, a portion of the deposited refractory metal oxide on the contact hole is transformed from non-conductive to conductive material, whereas the refractory metal oxide without a hydrogen plasma treatment or hot hydrogen treatment remains non-conductive. Therefore, a non-conductive refractory metal oxide layer can be used as a dielectric layer for a DRAM capacitor.
    Type: Grant
    Filed: October 15, 1998
    Date of Patent: January 25, 2000
    Assignee: United Microelectronics Corp.
    Inventors: Fu-Tai Liou, Water Lur