Patents Represented by Attorney Hoffman, Warnick, and D'Alessandro LLC

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  • Test fixture for evaluating RF identification system and related methods
    Patent number: 7102517
    Abstract: A test fixture for evaluating an RF identification system and related methods for evaluating an RF tag and/or an RF antenna, are disclosed. The test fixture provides predefined RF tag positions that can be used to test: read position, distance and antenna capability and adjustments. By placing an actual RF tag in each of the predefined positions, a read of the tag information can be performed. A three dimensional plot can then be established for the sensitivity field of the antenna. By placing the RF tag in various positions and orientations, the antenna can be adjusted until an optimum field is produced. The invention can also be used to determine RF tag performance within the optimized field.
    Type: Grant
    Filed: August 20, 2004
    Date of Patent: September 5, 2006
    Assignee: International Business Machines Corporation
    Inventors: Ray A. Reyes, David L. Schmoke, Edward Sherwood
  • Method of forming ladder-type gate structure for four-terminal SOI semiconductor device
    Patent number: 7101745
    Abstract: A ladder-type gate structure for a silicon-on-insulator (SOI) four-terminal semiconductor device is disclosed. The structure includes a gate having a first and second portion, a body region, which is under the first portion of the gate, a body contact, which is adjacent to the second portion of the gate, and a plurality of body contacts connecting the body region to the body contact through a drain region. The gate structure provides an independently controlled body region and includes a substantially uniform voltage across the body region in the SOI semiconductor device.
    Type: Grant
    Filed: December 3, 2004
    Date of Patent: September 5, 2006
    Assignee: International Business Machines Corporation
    Inventor: Paul A. Hyde
  • Mesh plane generation and file storage
    Patent number: 7096451
    Abstract: A method, system and program product implementing storage of a (power or ground) mesh plane file using a multiple line shape, possibly with the storage of lines also, to reduce file size. In addition, the invention implements an activate-substantial-portion-and-remove technique to generate mesh planes rather than the conventional additive approach, which improves the speed of designing the IC carriers. A resulting mesh plane design file may be as much as half the size of a file generated using the conventional line-by-line and storage approaches.
    Type: Grant
    Filed: September 9, 2003
    Date of Patent: August 22, 2006
    Assignee: International Business Machines Corporation
    Inventors: Alice L. Donaldson, Jason L. Frankel, John A. Ludwig, Kenneth A. Papae, Rafael Perez-Acevedo, C. Timothy Ryan, Paul R. Walling
  • White light emitting device and method
    Patent number: 7095056
    Abstract: A white light emitting device and method that generate light by combining light produced by a white light source with light produced by at least one supplemental light emitting diode (LED). The supplemental light can be used to adjust one or more properties of the generated light. Adjustments can be made to the generated light based on feedback.
    Type: Grant
    Filed: December 1, 2004
    Date of Patent: August 22, 2006
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Pranci{hacek over (s)}kus Vitta, Arturas Zukauskas, Remigijus Gaska, Michael Shur
  • Multiple supply gate array backfill structure
    Patent number: 7095063
    Abstract: A multiple supply gate array structure facilitated by the provision of a shared n-well and an isolated n-well is described. The gate array structure allows implementation of a single voltage circuit or a multiple voltage circuit. In addition, the gate array structure allows metal reprogram to provide standard logic functions, or special logic functions such as a buffer function for a signal crossing a voltage island boundary. Other special logic functions may include, for example, a level-shifter function or a fence-hold function.
    Type: Grant
    Filed: May 7, 2003
    Date of Patent: August 22, 2006
    Assignee: International Business Machines Corporation
    Inventors: John M. Cohn, Kevin M. Grosselfinger, William F. Smith, Paul S. Zuchowski
  • System, method and recordable medium for uploading documents over a network
    Patent number: 7095519
    Abstract: This invention relates to a system and method to upload and recover print jobs over a network. A client sends to a server a request for a specific document to be uploaded for transfer across a network. The sever creates an object to identify and process the request. The server sends a response to the client indicating that the request has been received and an associated object has been created. The server stores packets of the data document as they are uploaded and transmitted. Once the complete document has been uploaded and transferred to the server, it is stored in a network accessible data store.
    Type: Grant
    Filed: November 13, 2000
    Date of Patent: August 22, 2006
    Assignee: Mimeo.com, Inc.
    Inventors: Jeff Stewart, Jennifer R. Pinco, David Uyttendaele, Craig Jacobs, Doug Finke, Shawn A. Roberts
  • IC design density checking method, system and program product
    Patent number: 7093212
    Abstract: A system, method and program product for performing density checking of an IC design. The invention establishes an evaluation array for the IC design including an array element for each evaluation window of the IC design. The number of evaluation windows is based on a smallest necessary granularity. A single pass through shape data for the IC design is then conducted to populate each array element with a shape area for a corresponding evaluation window. Density checking is performed by iterating over the evaluation array using a sub-array. The sub-array may have the size of the preferred density design rule window. The invention removes the need for repetitive calculations, and results in a more efficient approach to density checking.
    Type: Grant
    Filed: March 26, 2004
    Date of Patent: August 15, 2006
    Assignee: International Business Machines Corporation
    Inventors: William F. DeCamp, Daniel J. Nickel
  • Method, system and program product for managing a size of a key management block during content distribution
    Patent number: 7092527
    Abstract: A method, system and program product for managing a size of a key management block (KMB) during content distribution is provided. Specifically, a first KMB corresponding to a first subtree of devices is received along with content as encrypted with a title key. If a size of the first KMB exceeds a predetermined threshold, a second subtree will be created. A second KMB corresponding to the second subtree of devices will then be generated. The second KMB contains an entry revoking the entire first subtree of devices and, as such, is smaller than the first KMD. Any compliant devices from the first subtree are migrated to the second subtree.
    Type: Grant
    Filed: April 18, 2002
    Date of Patent: August 15, 2006
    Assignee: International Business Machines Corporation
    Inventors: Eric M. Foster, Jeffrey B. Lotspiech, Florian Pestoni, Wilfred E. Plouffe, Jr., Frank A. Schaffa
  • Single request data transfer regardless of size and alignment
    Patent number: 7093058
    Abstract: A method, computer system and set of signals are disclosed allowing for communication of a data transfer, via a bus, between a master and a slave using a single transfer request regardless of transfer size and alignment. The invention provides three transfer qualifier signals including: a first signal including a starting byte address of the data transfer; a second signal including a size of the data transfer in data beats; and a third signal including a byte enable for each byte required during a last data beat of the data transfer. The invention is usable with single or multiple beat, aligned or unaligned data transfers. Usage of the three transfer qualifier signals provides the slave with how many data beats it will transfer at the start of the transfer, and the alignment of both the starting and ending data beats. As a result, the slave need not calculate the number of bytes it will transfer.
    Type: Grant
    Filed: October 7, 2005
    Date of Patent: August 15, 2006
    Assignee: International Business Machines Corporation
    Inventors: Victor R. Angsburg, James N. Dieffenderfer, Bernard C. Drerup, Richard G. Hofmann, Thomas A. Sartorius, Barry J. Wolford
  • Circuit power reduction using micro-electromechanical switches
    Patent number: 7091765
    Abstract: The invention provides micro-electromechanical switch (MEM) based designs for reducing the power consumption of logic blocks (e.g., latches) by isolating the logic blocks when they are non-operational. A power reduction circuit in accordance with the present invention comprises a logic block and at least one micro-electromechanical (MEM) switch for selectively disabling the logic block. MEM switches are provided for selectively: disconnecting the logic block from power; disconnecting the logic block from ground; providing a bypass line around the logic block; disconnecting an output of the logic block; and/or disconnecting an input of the logic block.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: August 15, 2006
    Assignee: International Business Machines Corporation
    Inventors: Mark R. Bilak, Thomas J. Fleischman
  • Expandable standoff connector with slit collar and related method
    Patent number: 7086896
    Abstract: An expanding standoff connector is disclosed including a collar having a slit through a wall of the collar, a tapered interior surface and an exterior surface configured to engage an interior of a mounting opening of the circuit board. A fastener including a threaded portion and a substantially cone shaped portion configured to mate with the tapered interior surface of the collar is placed within the collar and advanced to expand the collar to mount the circuit board. A related method for mounting a circuit board is also disclosed. Since the expansion is horizontal only (purely radial), a more uniform radial expansion from top-to-bottom of the collar is applied to the circuit board and a best-fit alignment between a circuit board and heatsink can be maintained.
    Type: Grant
    Filed: October 28, 2004
    Date of Patent: August 8, 2006
    Assignee: International Business Machines Corporation
    Inventors: David L. Edwards, Ronald L. Hering, David C. Long, Jason S. Miller
  • Method and system for searching for web content
    Patent number: 7089233
    Abstract: The present invention provides a method and system for searching for web content. Specifically, the present invention provides a system and method for retrieving web content from designated web pages and hyperlinks, indexing the retrieved web content in a local database, and searching the local database for desired web content. Retrieved content is indexed in the local database so that future access of the web content can be more efficient.
    Type: Grant
    Filed: September 6, 2001
    Date of Patent: August 8, 2006
    Assignee: International Business Machines Corporation
    Inventor: Michael James Osias
  • Programmable use of data extracted from common presentation files
    Patent number: 7089261
    Abstract: A system and method of retrieving a target set of data from a presentation file. The system comprises: an extractor that extracts data elements from the presentation file, associates a unique identifier to each data element, and stores each data element and associated identifier in an extraction object; and a formatter that selects the target set of the data from the extraction object based on a set of references in a target object. Each reference conforms to a predefined set of rules that allow, for instance, data elements to be addressed by page, object, row and column.
    Type: Grant
    Filed: July 25, 2002
    Date of Patent: August 8, 2006
    Assignee: International Business Machines Corporation
    Inventor: William J. Hladik, Jr.
  • Method of forming freestanding semiconductor layer
    Patent number: 7087506
    Abstract: A method of providing a freestanding semiconductor layer on a conventional SOI or bulk-substrate silicon device includes forming an amorphous or polycrystalline mandrel on a monocrystalline base structure. A conformal polycrystalline semiconductor layer is then formed on the mandrel and on the base structure, wherein the polycrystalline layer contacts the base structure. The polycrystalline semiconductor layer is then recrystallized so that it has a crystallinity substantially similar to that of the base structure. Thus, a freestanding semiconductor layer is formed with a high degree of control of the thickness and height thereof and maintaining a uniformity of thickness.
    Type: Grant
    Filed: June 26, 2003
    Date of Patent: August 8, 2006
    Assignee: International Business Machines Corporation
    Inventors: Brent A Anderson, Edward J Nowak, BethAnn Rainey
  • Integrated circuit design for signal integrity, avoiding well proximity effects
    Patent number: 7089513
    Abstract: A method, system and program product for designing an integrated circuit (IC) for signal integrity. The invention conducts a signal integrity analysis on an IC design; identifies any field effect transistor (FET) that causes a signal integrity failure in the case that the IC design fails the signal integrity analysis; and modifies an edge of a failing FET that is closer than a threshold distance to a well edge. The invention eliminates the manual, iterative procedure for determining the device causing a signal integrity failure due to well proximity effects.
    Type: Grant
    Filed: March 19, 2004
    Date of Patent: August 8, 2006
    Assignee: International Business Machines Corporation
    Inventors: Karen A. Bard, Ronald D. Rose, Michael H. Sitko
  • Gate electrode forming methods using conductive hard mask
    Patent number: 7084024
    Abstract: Methods related to formation of a gate electrode are disclosed that employ a conductive hard mask as a protective layer during a photoresist removal process. In preferred embodiments, the conductive hard mask includes a metal containing conductor or a metal silicide. The invention prevents process damage on the gate dielectric during wet and/or dry resist strip, and since the conductive hard mask cannot be etched in typical resist strip chemistries, the invention also protects a metal electrode under the hard mask. The steps disclosed allow creation of a multiple work function metal gate electrode, or a mixed metal and polysilicon gate electrode, which do not suffer from the problems of the related art.
    Type: Grant
    Filed: September 29, 2004
    Date of Patent: August 1, 2006
    Assignee: International Business Machines Corporation
    Inventors: Oleg Gluschenkov, Dae-Gyu Park
  • Performance measurement of device dedicated to phase locked loop using second order system approximation
    Patent number: 7084615
    Abstract: A method, system and program product to measure performance of a device dedicated to a phase locked loop (PLL). A resistor-inductor-capacitor (RLC) model is produced to simulate the PLL. The RLC model and the device to be measured are mapped together into a test circuit and the characteristics of the test circuit is analyzed to determine whether the device, if attached to the PLL represented by the RLC model, can meet the required standard of performance. This invention can be used to measure the performance of all kinds of devices attached to all kinds of PLLs.
    Type: Grant
    Filed: February 18, 2005
    Date of Patent: August 1, 2006
    Assignee: International Business Machines Corporation
    Inventors: Faraydon Pakbaz, Stephen D. Wyatt
  • System and method for probabilistic criticality prediction of digital circuits
    Patent number: 7086023
    Abstract: The present invention is a system and method for determining criticality probability of each node, edge and path of the timing graph of a digital circuit in the presence of delay variations. The delay of each gate or wire is assumed to consist of a nominal portion, a correlated random portion that is parameterized by each of the sources of variation and an independent random portion. Correlations are taken into account. Both early mode and late mode timing are included; both combinational and sequential circuits are handled; static CMOS as well as dynamic logic families are accommodated. The criticality determination complexity is linear in the size of the graph and the number of sources of variation. The invention includes a method for efficiently enumerating the critical path(s) that is/are most likely to be critical.
    Type: Grant
    Filed: September 19, 2003
    Date of Patent: August 1, 2006
    Assignee: International Business Machines Corporation
    Inventor: Chandramouli Visweswariah
  • Forming capping layer over metal wire structure using selective atomic layer deposition
    Patent number: 7084060
    Abstract: Methods of forming a capping layer over a metal wire structure of a semiconductor device are disclosed. In one embodiment, the method includes providing a partially fabricated semiconductor device having exposed surfaces of the metal (e.g., copper) wire structure and a dielectric around the metal wire structure. The exposed surface of the metal wire structure is then activated by forming a seed layer thereon. The capping layer is then formed over the exposed surface of the metal wire structure by performing a selective atomic layer deposition (ALD) of a capping layer material onto the metal wire structure. As an alternative, the dielectric may be masked off to further assist the selectivity of the ALD. The invention also includes a semiconductor structure including the metal wire structure having an atomic layer deposition capping layer over an upper surface thereof.
    Type: Grant
    Filed: May 4, 2005
    Date of Patent: August 1, 2006
    Assignee: International Business Machines Corporation
    Inventors: Toshiharu Furukawa, Steven J. Holmes, David V. Horak, Charles W. Koburger, III
  • System, method and program product for centrally managing agents
    Patent number: 7085764
    Abstract: A system, method and program product for centrally managing agents are provided. Specifically, under the present invention, master agents stored in a control database of a control system are scheduled to execute remote agents stored in remote databases of remote systems. Once executed by the master agents, the remote agents will implement functions thereto. By providing centralized management of agents in this manner, agent scheduling conflicts are prevented.
    Type: Grant
    Filed: May 13, 2002
    Date of Patent: August 1, 2006
    Assignee: International Business Machines Corporation
    Inventors: Matthew J. Bangel, David M. Filiberti, William M. Houston, James A. Martin, Jr., Eric J. Morin