Abstract: A solution for evaluating trust in a computer infrastructure is provided. In particular, a plurality of computing devices in the computer infrastructure evaluate one or more other computing devices in the computer infrastructure based on a set of device measurements for the other computing device(s) and a set of reference measurements. To this extent, each of the plurality of computing devices also provides a set of device measurements for processing by the other computing device(s) in the computer infrastructure.

Abstract: The invention includes a method and resulting structure for fabricating high performance vertical NPN and PNP transistors for use in BiCMOS devices. The resulting high performance vertical PNP transistor includes an emitter region including silicon and germanium, and has its PNP emitter sharing a single layer of silicon with the NPN transistor's base. The method adds two additional masking steps to conventional fabrication processes for CMOS and bipolar devices, thus representing minor additions to the entire process flow. The resulting structure significantly enhances PNP device performance.

Abstract: A system and method for efficiently walking a directed non-cyclic graph of hierarchical data using multiple analysis tools. The graph walking system comprises: a system for binding a plurality of graph observers to a graph, wherein each graph observer is further bound to a set of node patterns and a set of node observers; graph walking logic for systematically walking through nodes within the graph, wherein the graph walking logic can be instructed by a first pruning system not to walk a set of sub-nodes of an encountered node; and a second pruning system that can be instructed by a node observer bound with an associated graph observer to deactivate the associated graph observer until the set of sub-nodes for the encountered node has been walked. The first pruning system will cause the set of sub-nodes not to be walked only if all of the plurality of graph observers have been deactivated.

Abstract: A system and method for providing a driver for a multi-voltage island/core architecture of an integrated circuit chip are provided. A complementary metal oxide semiconductor (CMOS) inverter is built with a high threshold voltage p-channel field-effect transistor (hi-Vt PFET) and a regular threshold voltage n-channel field-effect transistor (NFET), which uses the maximum positive voltage supply (Vdd) on the chip. The threshold voltage of the hi-Vt PFET is determined based on the maximum Vdd, the Vdd of the Voltage island/core that drives the CMOS inverter, and a subthreshold leakage current requirement of the hi-Vt PFET.

Abstract: A state machine representation is provided that includes a plurality of nodes that are assigned a unique node identifier and an output value, and that are grouped into color segments. The nodes are interconnected by transitional vectors, with each transitional vector being assigned a unique value. Further, at least one of the nodes has a termination vector that leads to a termination point. To encrypt the set of data values, a start node is identified and any path of transitional vectors is be traversed from node to node. As each transitional vector is traversed, its corresponding unique value will be recorded in sequence. When a node is reached that has an output value that matches one of the set of data values, an invalid unique value is designated and recorded in sequence with the unique values.

Abstract: A method for load balancing traffic among routers in a data transmission system that includes a network, a set of routers, and a plurality of groups of servers. Each group of servers transfers its flow of data to the network through a first router, the address of which is assigned by a routing protocol. The load on the first router is compared periodically with a predetermined high threshold. If the load exceeds the high threshold, the priority of the first router is lowered in order to transfer the flow of data to a second router. If the load on the first router is subsequently found to be less that a predetermined low threshold, the priority of the first router is increased in order to transfer the flow of data from the second router back to the first router.

Abstract: A method, system and program product for migrating an integrated circuit (IC) design from a source technology without radical design restrictions (RDR) to a target technology with RDR, are disclosed. Also, a method, system and program product for migrating an integrated circuit design from a source technology without RDR to a target technology with RDR in which space may be reserved for late insertion of a feature and in which migration first occurs in a primary compaction direction having less tolerant ground rules.

Abstract: A method for treating an edge portion of a wafer with a plasma or select chemical formulation in order to enhance adhesion characteristics and inhibit delamination of a layer of material from the wafer surface only on the edge portion that is being treated. Alternatively, the method may be utilized to effectuate a cleaning of an edge portion of a wafer.

Abstract: A non-destructive in-situ elemental profiling of a layer in a set of layers method and system are disclosed. In one embodiment, a first emission of a plurality of photoelectrons is caused from the layer to be elementally profiled. An elemental profile of the layer is determined based on the emission. In another embodiment, a second emission of a plurality of photoelectrons is also received from the layer, and an elemental profile is determined by comparison of the resulting signals. A process that is altering the layer can then be controlled “on-the-fly” to obtain a desired material composition. Since the method can be employed in-situ and is non-destructive, it reduces turn around time and lowers wafer consumption. The invention also records the composition of all processed wafers, hence, removing the conventional statistical sampling problem.

Abstract: Methods are disclosed for reducing damage to an ultra-low dielectric constant (ULK) dielectric during removal of a planarizing layer such as a crosslinked polymer. The methods at least partially fill an opening with an at most lightly crosslinked polymer, followed by the planarizing layer. When the at most lightly crosslinked polymer and planarizing layer are removed, the at most lightly crosslinked polymer removal is easier than removal of the planarizing layer, i.e., crosslinked polymer, and does not damage the surrounding dielectric compared to removal chemistries used for the crosslinked polymer.

Abstract: A bipolar transistor with raised extrinsic base and selectable self-alignment between the extrinsic base and the emitter is disclosed. The fabrication method may include the formation of a predefined thickness of a first extrinsic base layer of polysilicon or silicon on an intrinsic base. A dielectric landing pad is then formed by lithography on the first extrinsic base layer. Next, a second extrinsic base layer of polysilicon or silicon is formed on top of the dielectric landing pad to finalize the raised extrinsic base total thickness. An emitter opening is formed using lithography and RIE, where the second extrinsic base layer is etched stopping on the dielectric landing pad. The degree of self-alignment between the emitter and the raised extrinsic base is achieved by selecting the first extrinsic base layer thickness, the dielectric landing pad width, and the spacer width.

Abstract: Automated tool recipe verification and correction are disclosed. A tool recipe is intercepted during uploading or downloading of the tool recipe. A determination whether an associated parameter verification set (PVS) template for the tool recipe exists is performed, and if it exists, a determination whether to verify the tool recipe is performed. Each parameters of the tool recipe having an auditable corresponding parameter is compared to the auditable corresponding parameter of the associated PVS template. Where no non-matching parameter sets exist, the tool recipe is verified; otherwise, a determination as to whether of all of the non-matching parameter sets are indicated as modifiable in the associated PVS template is made. If all of the parameters of the non-matching parameter sets are modifiable, then they are modified to match the respective auditable corresponding parameter and the tool recipe is verified, otherwise, the verification is inhibited.

Abstract: The present invention provides an improved control methodology for maximum power point tracking (MPPT), anti-islanding, and output current regulation for distributed generation sources connected to a utility grid. The control includes enhancements for MPPT and regulating the inverter output-current that is sourced into the utility grid. In addition, the functions associated with MPPT, anti-islanding detection and output current regulation are integrated together; the MPPT algorithm operates in conjunction with the anti-islanding detection, and the output current regulation operates in conjunction with the MPPT algorithm.

Abstract: Methods are disclosed for forming dual stressed layers in such a way that both undercutting and an undesirable residual spacer of the first-deposited stressed layer are prevented. In one embodiment, a method includes forming a first stressed silicon nitride layer over the NFET and the PFET, forming a sacrificial layer over the first stressed silicon nitride layer such that the sacrificial layer is thinner over substantially vertical surfaces than over substantially horizontal surfaces, forming a mask over a first one of the NFET and the PFET, removing the first stressed silicon nitride layer over a second one of the NFET and the PFET, and forming a second stressed silicon nitride layer over the second one of the NFET and the PFET. The sacrificial layer prevents undercutting and forming of an undesirable residual spacer during removal of the first-deposited stressed layer.

Abstract: A system for supporting a cylindrical object such as a storage tank using a plurality of supports. Each support may be a foot, having a curved portion adjacent to the cylindrical object and a base section. The feet may be mounted with their curved portions adjacent to the sides of the tank and the base section may be attached to a flexible base, which may be rolled or folded for easy storage when not in use. Furthermore, the support may be a portion of the base itself, folded toward the cylindrical object or folded as a flap from the center region toward the outer edge. The independent nature of the supports and their adjustability with respect to the base makes them suitable for use with tanks of various sizes. The independent nature of the supports also makes them suitable for use on uneven ground.

Abstract: The invention relates to a device for determining the path of an in particular metallic target, with at least two detection devices so positioned along a path to be monitored that the sensitivity curves of immediately adjacent detection devices at least partly overlap, the detection devices in each case having at least one inductance coil and at least one oscillator and as a function of a damping of the oscillator by the target supply a distance signal, with at least one converting device operatively connected to the detection devices for converting the dampings detected by the detection devices into analog signals, particularly current and/or voltage signals, and with at least one evaluating device operatively connected to the converting device or devices for determining and reading out a local position of the target from the analog signals going back to the detection devices.

Abstract: An RNIC implementation that performs direct data placement to memory where all segments of a particular connection are aligned, or moves data through reassembly buffers where all segments of a particular connection are non-aligned. The type of connection that cuts-through without accessing the reassembly buffers is referred to as a “Fast” connection because it is highly likely to be aligned, while the other type is referred to as a “Slow” connection. When a consumer establishes a connection, it specifies a connection type. The connection type can change from Fast to Slow and back. The invention reduces memory bandwidth, latency, error recovery using TCP retransmit and provides for a “graceful recovery” from an empty receive queue. The implementation also may conduct CRC validation for a majority of inbound DDP segments in the Fast connection before sending a TCP acknowledgement (Ack) confirming segment reception.

Abstract: An improved solution for designing and/or evaluating a circuit is provided. A rule violation can be detected in design data for the circuit and a prediction can be generated based on an adjustment to the design data. For example, multiple predictions can be generated based on an adjustment window for an adjustable parameter in the design data. The predictions can be displayed to a user, who can determine a desired modification to the design data. The modification can be implemented by the user and/or automatically implemented by a circuit design tool.

Abstract: Method, system and program product for determining a critical area in a region of an integrated circuit layout using Voronoi diagrams and shape biasing. The method includes the steps of generating a biased Voronoi diagram based on a layout geometry of the region and incorporating a shape bias; and determining the critical area for the region using the biased Voronoi diagram.

Abstract: A system and method of identifying foreground segments in a JPEG image. The method includes the steps of: selecting a block in the JPEG image; extracting a set of DCT coefficients from the block, wherein the set comprises the first N AC components of the block; computing a sum of the set of DCT coefficients; and analyzing the sum to determine if the block is part of a foreground segment.