Patents Represented by Attorney Horizon IP Pte Ltd
  • Patent number: 8338280
    Abstract: Embodiments relate to a method for fabricating nano-wires in nano-devices, and more particularly to nano-device fabrication using end-of-range (EOR) defects. In one embodiment, a substrate with a surface crystalline layer over the substrate is provided and EOR defects are created in the surface crystalline layer. One or more fins with EOR defects embedded within is formed and oxidized to form one or more fully oxidized nano-wires with nano-crystals within the core of the nano-wire.
    Type: Grant
    Filed: July 8, 2010
    Date of Patent: December 25, 2012
    Assignees: GLOBALFOUNDRIES Singapore Pte. Ltd., Nanyang Technological University
    Inventors: Dexter Tan, Kin Leong Pey, Sai Hooi Yeong, Yoke King Chin, Kuang Kian Ong, Chee Mang Ng
  • Patent number: 8339449
    Abstract: A method of forming a device is presented. The method includes providing a substrate containing at least a partially formed device thereon. The device comprises at least one defect site. A pixilated image of the defect site is acquired, and each pixel comprises a grey level value (GLV). Surrounding noises of the defect site is eliminated. A point of the image is identified as the center of the defect. A plurality of iterations to exclude outer edge pixels surrounding the center of the defect image is performed. The defect is categorized as a killer or non-killer defect.
    Type: Grant
    Filed: August 7, 2009
    Date of Patent: December 25, 2012
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Barbara Fong Chin Lim, Keng Heng Lai, Tanya Yang, Victor Seng Keong Lim, Fang Hong Gn, Liang Choo Hsia
  • Patent number: 8334567
    Abstract: First example embodiments comprise forming a stress layer over a MOS transistor (such as a LDMOS Tx) comprised of a channel and first, second and third junction regions. The stress layer creates a stress in the channel and the second junction region of the Tx. Second example embodiments comprise forming a MOS FET and at least a dummy gate over a substrate. The MOS is comprised of a gate, channel, source, drain and offset drain. At least one dummy gate is over the offset drain. A stress layer is formed over the MOS and the dummy gate. The stress layer and the dummy gate improve the stress in the channel and offset drain region.
    Type: Grant
    Filed: November 1, 2010
    Date of Patent: December 18, 2012
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Sanford Chu, Yisuo Li, Guowei Zhang, Purakh Raj Verma
  • Patent number: 8324011
    Abstract: The present invention provides a method of annealing a semiconductor by applying a temperature-dependant phase switch layer to a semiconductor structure. The temperature-dependant phase switch layer changes phase from amorphous to crystalline at a predetermined temperature. When the semiconductor structure is annealed, electromagnetic radiation passes through the temperature-dependant phase switch layer before reaching the semiconductor structure. When a desired annealing temperature is reached the temperature-dependant phase switch layer substantially blocks the electromagnetic radiation from reaching the semiconductor structure. As a result, the semiconductor is annealed at a consistent temperature across the wafer. The temperature at which the temperature-dependant phase switch layer changes phase can be controlled by an ion implantation process.
    Type: Grant
    Filed: September 11, 2007
    Date of Patent: December 4, 2012
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Chyiu Hyia Poon, Alex See, Mei Sheng Zhou
  • Patent number: 8324031
    Abstract: A method of forming a device is presented. The method includes providing a structure having first and second regions. A diffusion barrier is formed between at least a portion of the first and second regions. The diffusion barrier comprises cavities that reduce diffusion of elements between the first and second regions.
    Type: Grant
    Filed: June 24, 2008
    Date of Patent: December 4, 2012
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Shyue Seng Tan, Lee Wee Teo, Yung Fu Chong, Elgin Quek, Sanford Chu
  • Patent number: 8321442
    Abstract: Described herein is a technology for facilitating searching and matching of data. In some implementations, an input data string, including one or more ideographic elements, is received and converted to a Latin-based input data string. One or more input keys may be generated based on the Latin-based input data string. A reference database may be searched for one or more candidate records indexed by at least one of the one or more input keys. If the one or more candidate records are found, a match score is determined for the one or more candidate records.
    Type: Grant
    Filed: September 6, 2010
    Date of Patent: November 27, 2012
    Assignee: Business Objects Software Limited
    Inventor: Xinrong Huang
  • Patent number: 8293545
    Abstract: Test structures including test trenches are used to define critical dimension of trenches in a via level of an integrated circuit to produce substantially the same depth. The trenches are formed at the periphery of the IC to serve as guard rings.
    Type: Grant
    Filed: October 29, 2007
    Date of Patent: October 23, 2012
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Hai Cong, Yan Shan Li, Chun Hui Low, Yelehanka Ramachandramurthy Pradeep, Liang Choo Hsia
  • Patent number: 8288800
    Abstract: A method of forming a device is disclosed. The method includes providing a substrate having an active area. A gate is formed on the substrate. First and second current paths through the gate are formed. The first current path serves a first purpose and the second current path serves a second purpose. The gate controls selection of the current paths.
    Type: Grant
    Filed: January 4, 2010
    Date of Patent: October 16, 2012
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Ming Zhu, Chun Shan Yin, Elgin Quek, Shyue Seng Tan
  • Patent number: 8289508
    Abstract: A method of forming a device is disclosed. The method includes providing a substrate and processing a layer of the device on the substrate. The layer is inspected with an inspection tool for defects. The inspection tool is programmed with an inspection recipe determined from studying defects programmed into the layer at known locations.
    Type: Grant
    Filed: November 19, 2009
    Date of Patent: October 16, 2012
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Victor Seng Keong Lim, Rachel Yie Fang Wai, Fang Hong Gn, Liang Choo Hsia
  • Patent number: 8288235
    Abstract: A device having a self-aligned body on a first side of a gate is disclosed. The self-aligned body helps to achieve very low channel length for low Rdson. The self-aligned body is isolated, enabling to bias the body at different bias potentials. The device may be configured into a finger architecture having a plurality of transistors with commonly coupled, sources, commonly coupled gates, and commonly coupled drains to achieve high drive current outputs.
    Type: Grant
    Filed: October 20, 2010
    Date of Patent: October 16, 2012
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventor: Purakh Raj Verma
  • Patent number: 8288825
    Abstract: A structure and method for forming raised source/drain structures in a NFET device and embedded SiGe source/drains in a PFET device. We provide a NFET gate structure over a NFET region in a substrate and PFET gate structure over a PFET region. We provide NFET SDE regions adjacent to the NFET gate and provide PFET SDE regions adjacent to the PFET gate. We form recesses in the PFET region in the substrate adjacent to the PFET second spacers. We form a PFET embedded source/drain stressor in the recesses. We form a NFET S/D epitaxial Si layer over the NFET SDE regions and a PFET S/D epitaxial Si layer over PFET embedded source/drain stressor. The epitaxial Si layer over PFET embedded source/drain stressor is consumed in a subsequent salicide step to form a stable and low resistivity silicide over the PFET embedded source/drain stressor.
    Type: Grant
    Filed: May 17, 2010
    Date of Patent: October 16, 2012
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Yung Fu Chong, Zhijiong Luo, Joo Chan Kim, Judson Robert Holt
  • Patent number: 8274115
    Abstract: A hybrid orientation substrate includes a base substrate having a first orientation, a first surface layer having a first orientation disposed on the base substrate in a first region, and a second surface layer disposed on the base substrate in a second region. The second surface layer has an upper sub-layer having a second orientation, and a lower sub-layer between the base substrate and the upper sub-layer. The lower sub-layer having a first stress induces a second stress on the upper sub-layer.
    Type: Grant
    Filed: March 19, 2008
    Date of Patent: September 25, 2012
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Lee Wee Teo, Chung Woh Lai, Johnny Widodo, Shyue Seng Tan, Shailendra Mishra, Zhao Lun, Yong Meng Lee, Jeffrey Chee
  • Patent number: 8268733
    Abstract: A method of forming a device is presented. The method includes providing a wafer having an active surface and dividing the wafer into a plurality of portions. The wafer is selectively processed by localized heating of a first of the plurality of portions. The wafer is then repeatedly selectively processed by localized heating of a next of the plurality of portions until all plurality of portions have been selectively processed.
    Type: Grant
    Filed: August 7, 2009
    Date of Patent: September 18, 2012
    Assignees: Nanyang Technological University, National University of Singapore, Globalfoundries Singapore Pte. Ltd.
    Inventors: Dexter Tan, Chee Chong Lim, Sai Hooi Yeong, Chee Mang Ng
  • Patent number: 8264088
    Abstract: A semiconductor device includes a substrate having a dielectric layer and a device layer on the substrate. The device layer has an opening. First and second sublayers are disposed on the device layer and line the opening. The second sublayer serves as a stop layer for planarization to provide a substantially planarized top surface for the semiconductor device.
    Type: Grant
    Filed: July 11, 2011
    Date of Patent: September 11, 2012
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Sin Leng Lim, In Ki Kim, Jong Sung Park, Min Hwan Kim, Wei Lu
  • Patent number: 8247272
    Abstract: A semiconductor package and a method for constructing the package are disclosed. The package includes a substrate and a die attached thereto. A first contact region is disposed on the substrate and a second contact region is disposed on the die. The first contact region, for example, comprises copper coated with an OSP material. A copper wire bond electrically couples the first and second contact regions. Wire bonding includes forming a ball bump on the first contact region having a flat top surface. Providing the flat top surface is achieved with a smoothing process. A ball bond is formed on the second contact region, followed by stitching the wire onto the flat top surface of the ball bump on the first contact region.
    Type: Grant
    Filed: June 22, 2009
    Date of Patent: August 21, 2012
    Assignee: United Test and Assembly Center Ltd.
    Inventors: Yong Chuan Koh, Jimmy Siat, Jeffrey Nantes Salamat, Lope Vallespin Pepito, Jr., Ronaldo Cayetano Calderon, Rodel Manalac, Pang Hup Ong, Kian Teng Eng
  • Patent number: 8242872
    Abstract: Embodiments of the invention provide a transformer comprising: a first coil element having a transverse axis along a transverse direction, the first coil element having p turns where p is greater than or equal to 1; and a second coil element having a transverse axis generally parallel to the transverse axis of the first coil element, the second coil element having n turns, where n is greater than or equal to 5p; wherein the first and second coil elements are arranged to provide electromagnetic coupling between the coil elements along a portion of a length of the second coil element in both a transverse direction parallel to the transverse axes and a lateral direction, wherein the lateral direction is a direction normal to the transverse axes.
    Type: Grant
    Filed: July 19, 2007
    Date of Patent: August 14, 2012
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Chee Chong Lim, Kok Wai Chew, Kiat Seng Yeo, Suh Fei Lim, Manh Anh Do, Lap Chan
  • Patent number: 8236688
    Abstract: A method of manufacture of an integrated circuit system includes: providing a substrate including an active device; forming a through-silicon-via into the substrate; forming an insulation layer over the through-silicon-via to protect the through-silicon-via; forming a contact to the active device after forming the insulation layer; and removing the insulation layer.
    Type: Grant
    Filed: June 13, 2011
    Date of Patent: August 7, 2012
    Assignee: Globalfoundries Singapore Pte. Ltd.
    Inventors: Pradeep Ramachandramurthy Yelehanka, Denise Tan, Chung Meng Lek, Thomas Thiam, Jeffrey C. Lam, Liang-Choo Hsia
  • Patent number: 8237531
    Abstract: An inductor circuit with high quality (Q) factor includes a primary inductor and a compensation sub-circuit. The compensation sub-circuit is electrically isolated from the primary inductor. The compensation sub-circuit is magnetically coupled with the primary inductor to compensate the loss in the primary inductor.
    Type: Grant
    Filed: December 31, 2007
    Date of Patent: August 7, 2012
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Ping Qiu, Chirn Chye Boon, Johnny Kok Wai Chew, Kiat Seng Yeo, Manh Anh Do, Lap Chan, Suh Fei Lim
  • Patent number: 8236678
    Abstract: A device that includes a substrate with an active region is disclosed. The device includes a gate disposed in the active region and tunable sidewall spacers on sidewalls of the gate. A profile of the tunable sidewall spacers includes upper and lower portions in which width of the spacers in the upper portion is reduced at a greater rate than the lower portion.
    Type: Grant
    Filed: December 17, 2008
    Date of Patent: August 7, 2012
    Assignee: Globalfoundries Singapore Pte. Ltd.
    Inventors: Ramachandramurthy Pradeep Yelehanka, Shailendra Mishra, Sripad Nagarad
  • Patent number: 8222130
    Abstract: A method of forming a device is presented. The method includes providing a substrate prepared with an active device region. The active device region includes gate stack layers of a gate stack including at least a gate electrode layer over a gate dielectric layer. A first mask is provided on the substrate corresponding to the gate. The substrate is patterned to at least remove portions of a top gate stack layer unprotected by the first mask. A second mask is also provided on the substrate with an opening exposing a portion of the first mask and the top gate stack layer. A channel well is formed by implanting ions through the opening and gate stack layers into the substrate.
    Type: Grant
    Filed: July 10, 2009
    Date of Patent: July 17, 2012
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Guowei Zhang, Purakh Raj Verma