Abstract: An efficient manufacturing automation system and method is described. The system and method include bays, with each bay having a group of tools. Temporary storage locations are provided. A transport system facilitates movement of materials from the tools. The system and method enable direct transfer of materials from a first tool to a second tool or transfer of materials from a first tool to a temporary storage location when a second tool is unavailable.

Abstract: A structure and method of fabrication of a semiconductor device having a stress relief layer under a stress layer in one region of a substrate. In a first example, a stress relief layer is formed over a first region of the substrate (e.g., PFET region) and not over a second region (e.g., NFET region). A stress layer is over the stress relief layer in the first region and over the devices and substrate/silicide in the second region. The NFET transistor performance is enhanced due to the overall tensile stress in the NFET channel while the degradation in the PFET transistor performance is reduced/eliminated due to the inclusion of the stress relief layer. In a second example embodiment, the stress relief layer is formed over the second region, but not the first region and the stress of the stress layer is reversed.

Abstract: A chromeless phase shift mask and Method for making and using. The A chromeless phase shift mask is used to pattern contact holes. The chromeless phase shift mask preferably comprises: a first phase shift region and a second phase shift region; the first region is comprised of a unit cell which is comprised of a rectangular center section and at least three rectangular sections (legs) outwards extending from the rectangular center section. The second region is adjacent to said first region. The interference between the first and second phase shift regions creates a contact hole pattern.

Abstract: Embodiments of the invention provide an integrated circuit structure comprising: a substrate; a shield structure comprising a shield member and a ground strap formed on the substrate, wherein the shield member comprises a non-metallic portion, and the ground strap comprises a metallic portion.

Abstract: An embodiment of fabrication of a variable work function gates in a FUSI device is described. The embodiment uses a work function doping implant to dope the polysilicon to achieve a desired work function. Selective epitaxy growth (SEG) is used to form silicon over the source/drain regions. The doped poly-Si gate is fully silicided to form fully silicided gates that have a desired work function. We provide a substrate having a NMOS region and a PMOS region. We form a gate dielectric layer and a gate layer over said substrate. We perform a (gate Vt) gate layer implant process to implant impurities such as P+, As+, B+, BF2+, N+, Sb+, In+, C+, Si+, Ge+ or Ar+ into the gate layer gate in the NMOS gate regions and said PMOS gate regions. We form a cap layer over said gate layer. We pattern said cap layer, said gate layer and said gate dielectric layer to form a NMOS gate and a PMOS gate. Spacers are formed and S/D regions are formed. A metal is deposited over said substrate surface.

Abstract: A MOS varactor includes a shallow PN junction beneath the surface of the substrate of a MOS structure. In depletion mode, the depletion region of the MOS structure merges with the depletion region of the shallow PN junction. This increases the total width of the depletion region of the MOS varactor to reduce Cmin.

Abstract: A first example embodiment provides a method of removing first spacers from gates and incorporating a low-k material into the ILD layer to increase device performance. A second example embodiment comprises replacing the first spacers after silicidation with low-k spacers. This serves to reduce the parasitic capacitances. Also, by implementing the low-k spacers only after silicidation, the embodiments' low-k spacers are not compromised by multiple high dose ion implantations and resist strip steps. The example embodiments can improve device performance, such as the performance of a rim oscillator.

Abstract: A method for forming a device with both PFET and NFET transistors using a PFET compressive etch stop liner and a NFET tensile etch stop liner and two anneals in a deuterium containing atmosphere. The method comprises: providing a NFET transistor in a NFET region and a PFET transistor in a PFET region. We form a NFET tensile contact etch-stop liner over the NFET region. Then we perform a first deuterium anneal. We form a PFET compressive etch stop liner over the PFET region. We form a (ILD) dielectric layer with contact openings over the substrate. We perform a second deuterium anneal. The temperature of the second deuterium anneal is less than the temperature of the first deuterium anneal.

Abstract: An embodiment of the invention shows a process to form a damascene opening preferably without hardmask overhang or dielectric layer undercut/void. The low-k dielectric material can be sandwiched in two hardmask films to form the dielectric film through which an interconnect opening is etched. A first example embodiment comprises the following. We form a lower interconnect and an insulating layer over a semiconductor structure. We form a first hardmask a dielectric layer, and a second hardmask layer, over the lower interconnect and insulating layer. We etch a first interconnect opening in the first hardmask, the dielectric layer and the second hardmask layer. Lastly, we form an interconnect in the first interconnect opening.

Abstract: An electromechanical device includes a support structure formed by attaching inner surfaces of second and third substrates to a first substrate. The support structure includes at least one cavity between the second and third layers. An electromechanical active element is provided on an outer surface of at least one of the second or third layers.

Abstract: A non-volatile memory cell includes an access and a storage transistor coupled in series. The memory cell is formed on a thin gate well tailored for transistors with thin gate dielectrics. The access transistor is a hybrid transistor which includes a gate with a thick gate dielectric layer formed on the thin gate well.

Abstract: Some example embodiments of the invention provide a method to improve the performance of MOS devices by increasing the stress in the channel region. An example embodiment for a NMOS transistor is to form a tensile stress layer over a NMOS transistor. A heavy ion implantation is performed into the stress layer and then an anneal is performed. This increases the amount of stress from the stress layer that the gate retains/memorizes thereby increasing device performance.

Abstract: In an non-limiting example, we provide a substrate having a cell region, and non-cell regions. We form a tunneling dielectric layer, a charge storing layer, a top insulating layer (e.g., ONO), over the substrate. Then we form a conductive pad layer over the top insulating layer. We form isolation trenches in the pad layer, the charge storing layer and the tunneling dielectric layer and into the substrate. We form isolation regions in the isolation trenches. We remove the pad layer, charge storing layer and the tunneling dielectric layer in the non-cell regions. We form a gate layer over the pad layer and the substrate surface. We complete to form the memory (e.g., SONOS) device in the cell region and other devices in the non-cell regions of the substrate.

Abstract: A method of filling gaps in dielectric layers is disclosed. A wafer is provided having a dielectric layer containing gaps to be filled with copper, some of the gaps, denoted deeper gaps, having aspect ratios so large that filling these gaps with copper using ECP could result in pinhole like voids. A blanket conformal metal barrier layer is formed and the wafer is then submerged in a solution to electroless plate a blanket conformal copper seed layer. A partial filling of deeper gaps with copper reduces the effective aspect ratios of the deeper gaps to the extent that ECP could be used to complete the copper filling of the gaps without forming pinhole like voids. ECP is then used to complete the copper filling of the gaps. The wafer is annealed and CMP performed to planarize the surface, giving rise to a structure in which the gaps are filled with copper and are separated by the dielectric layer.

Abstract: A device structure and method for forming graded junction using a implant process. Embodiments of the invention comprise implanting ions into said silicon substrate to form doped regions adjacent to said gate. The orientation of the channel region in the Si crystal structure (channel direction <100>) in combination with the large angle tilt and twist implant process produce doped regions that have a more graded junction. The orientation and implant process creates more channeling of ions. The channeling of ions creates a more graded junction. When implemented on a HV MOS TX, the graded junction of the LDD increases the breakdown voltage. Another embodiment is a FET with an annular shaped channel region.

Abstract: Embodiments for FET devices with stress on the channel region by forming stressor regions under the source/drain regions or the channel region and forming a selective strained Si using lateral epitaxy over the stressor regions. In a first example embodiment, a lateral epitaxial layer is formed over a stressor region under a channel region of an FET. In a second example embodiment, a lateral S/D epitaxial layer is formed over S/D stressor region under the source/drain regions of an FET. In a third example embodiment, both PFET and NFET devices are formed. In the PFET device, a lateral S/D epitaxial layer is formed over S/D stressor region under the source/drain regions. In the NFET device, the lateral epitaxial layer is formed over a stressor region under a channel region of the NFET.

Abstract: An integrated transformer structure includes a first coil element associated with a transverse axis, the first coil element having at least one turn. The first coil element includes a first portion provided on a first lateral level, and a second portion provided on a second lateral level. The first and second lateral levels being mutually spaced apart along said transverse axis. The first and second portions being displaced laterally from said axis by different respective distances. At least one crossover portion of the first coil element, in which the first coil element being configured to provide a conducting path through at least a portion of the first portion of the first coil element to the crossover portion, through the crossover portion and subsequently through at least a portion of the second portion of the first coil element, in which any change of flow direction along said path is less than 90° in a lateral direction.

Abstract: The present invention relates to integrated circuits. In particular, but not exclusively, the invention relates to a method and apparatus for connecting elements of integrated circuits with interconnects having one or more voids formed between adjacent interconnects. Embodiments of the invention provide apparatus for connecting elements in an integrated circuit device, comprising: at least one interconnect comprising one or more sidewalls; an interconnect sidewall spacer element arranged to provide structural support to the interconnect and formed on at least one of the interconnect sidewalls; and at least one void adjacent said interconnect and extending from the sidewall spacer element.

Abstract: The first and second example embodiments are Pattern Fidelity Optimization Procedures for a Multiple Exposure Scheme. In the third example embodiment, the aperatures from the multiple exposure system can be combined into a single aperture by adding the apertures and modulating the relative transmission thru the respective apertures to match the prescribed dose split determined in above in the first embodiment.

Abstract: A method of forming a barrier layer and cap comprised of CuSiN for an interconnect. We provide an interconnect opening in a dielectric layer over a semiconductor structure. We form a CuSiN barrier layer over the sidewalls and bottom of the interconnect opening by reacting with the first copper layer. We then form an interconnect over the CuSiN layer filling the interconnect opening. We can form a CuSiN cap layer on the top surface of the interconnect.