Abstract: An intermodulation distortion limiter controls the ratio of average power to peak envelope power in the output of a linear power amplifier and this protects against excess non-linearity by reducing the drive power when the ratio exceeds a similar ratio associated with the incoming RF signal.

Abstract: A flip-flop receives clock pulses of frequency F and is alternately set and reset on alternate inverted third clock pulse edges by logic responsive to the clock pulses and to the output of the flip-flop. The logic includes a second flip-flop and a pair of gates which maintain the set and reset states of the first flip-flop for two consecutive clock pulse edges between set and reset transitions to provide symmetrical output pulses from the first flip-flop of frequency 1/3F with a substantially 50% duty cycle.

Abstract: A servo mechanism is illustrated whereby movement of a motor device subsequent to application of drive signals is sensed to determine erroneous movement due to detrimental forces such as spring action. Compensating signals are generated to modify the drive signals whereby the motor is accurately step positioned with each set of drive pulses.

Abstract: A subinterval sampler is provided for sampling short duration analog input signal pulses with slower speed processing hardware than would otherwise be required. The peak value of the input signal is detected during each sampling interval regardless of the absolute times at which peaks occur, an no input signal peak is missed. A pair of parallel peak detectors have active intervals overlapped by a duration longer than the rise time of the peak detectors, and have nonconcurrent inactive intervals for clearing. The outputs of the peak detectors are alternately switched into sample and hold circuitry at a switching rate equal to the sampling rate but staggered such that switching times occur midway in the sampling intervals.

Abstract: A balun coupled microwave frequency converter is provided by a mixer using a single diode pair with one port balanced and the other port unbalanced. The balanced port is provided by first and second coplanar conductors extending toward a common area and juxtaposed in spaced parallel relation with a transmission line interacting therewith to couple a field balanced between the first and second conductors across the common area. The unbalanced port to the mixer is provided by a third conductor. The diode pair is connected in series between the first and second conductors, and a point between the diodes is connected to the third conductor. One implementation is an up converter with an LO and an IF signal applied on the third conductor and input to the mixer to generate an RF signal between the first and second conductors and hence an induced output RF signal on the transmission line.

Abstract: A plurality of conferencers are connected to a common bus. Each conferencer has a plurality of accumulators each for outputting a CVSD conference. Each conferencer selectively places any one or all or any combination of a plurality of inputs in any one or all or any combination of its accumulators independently of each other and independently of the accumulators in the remaining conferencers. Inputs may be selectively scaled to provide different volume levels for different conferees.

Abstract: A split phase delay equalizer is provided which reduces loss without resorting to high values of load impedance. The equalizer has a pair of parallel circuit branches, one of which is through the base and collector of a transistor, and the other through a reactance network connected between the collector and base of the transistor.

Abstract: A prescription attenuator comprising a plurality of cascaded L-pad sections coupled together to form an attenuator network wherein each cascaded section includes a single pole switch for activating its respective section. The network impedance values are selected so that single L-pad section activations produce actual attenuations slightly more than an ideal level of attenuation wherein multiple section activations tend to keep the error evenly distributed about the ideal level of attenuation.

Abstract: A split phase delay equalizer is constructed using a single transformer. An adjustment for Q loss is provided by a flat loss shift in the amplitude response of the equalizer down to a level at or below the lowest Q loss dip level.

Abstract: A wide band, feedforward, power amplifier circuit has greater stability when quadrature hybrid devices are used to match the output impedance of the power amplifier with the load.

Abstract: An apparatus is disclosed for selecting between multiple radio frequency circuits such as low pass filters. Each of the circuits is mounted on a printed circuit board, with first and second terminals printed on the board. Each of the terminals has a raised electrical contact on it. Associated with the first terminals of the circuits is a first printed strip transmission line with raised contacts spaced along it, each contact near a corresponding contact on one of the first terminals of the circuits. A second printed transmission line is similarly arranged. External connection to the apparatus is made at one end of each of the transmission lines. To select one of the circuits, the first and second terminals of the circuit are connected to the corresponding transmission lines, by a switch which moves a resilient conducting member against the pairs of raised contacts of the transmission lines and the circuit terminals.

Abstract: The performance of a wide band feedforward power amplifier circuit is enhanced when a phase intercept distortion compensation circuit is used to provide phase and amplitude matching between the signal amplifier and the feedforward path.

Abstract: A digital circuit receives symmetrical clock pulses of frequency F and outputs symmetrical pulses of frequency 1/3 F. A divide by one and one-half circuit clocks a divide by two flip-flop resulting in a symmetrical divide by three output. The divide by one and one-half circuit includes a pair of JK flip-flops and logic gates which receive clock pulses of frequency F and generate a plurality of staggered signal streams with nonsymmetrical pulses of frequency 1/3 F and a duty cycle of substantially 33%. The input clock pulses are gated against two of these streams to provide an output pulse during the first half of the duty portion of a cycle of one of the streams, and another output pulse during the second half of the duty portion of a cycle of the other stream, to provide an output frequency of 2/3 F which then clocks the divide by two flip-flop.

Abstract: An improvement is disclosed for a computer system wherein a high speed peripheral device sends data words of a first length to a memory which operates with a word of a greater length, for example, twice the data word length. The improvement includes an apparatus for identifying pairs of data words which belong together in a single memory word. Then, a pair of the data words can be written to memory in a single operation, rather than two separate write operations.

Abstract: An AC to DC converter that utilizes a split capacitor, half bridge, DC to DC converter compensates for unequal voltages across each member of a split capacitor bank. A voltage balance control circuit senses any differences in voltages across the member capacitors and generates an error correcting signal for modifying steering signals to an inverter that is used to convert a DC signal from the half bridge DC to DC converter to a high frequency pulse width modulated AC signal by alternately placing each member of the split capacitor bank and consequently their stored energy across the output terminals of the inverter. The error signal causes the steering signals to connect the member capacitor with the larger sensed voltage across the output terminals for a relatively larger period of time than the capacitor with the lesser sensed voltage.

Abstract: A muldem (100) has a monitor (101) for testing data path failures through the muldem (100) by comparing the latter's input and output. The monitor (101) tests itself by injecting errors into one of the compared data streams for detection thereof if the monitor (101) and comparing means (806, FIG. 13a and b) is operating properly. Error injection is particularly accomplished by an error generator (922, FIG. 14) synchronously clocked with a data stream (904) through an exclusive OR gate (938). The error generator (922) includes a free running gated oscillator (924) and a pair of ganged flip-flops (926, 928) toggled by a clock signal (936) recovered from the data stream (904).

Abstract: A voltage regulator for a DC power supply senses the current in the return line of the power supply and compares the sensed current to a threshold that is generated within the regulator section of the power supply. When the sensed current exceeds the threshold, a detector circuit will sense the threshold being exceeded and override the voltage control circuit that is used to regulate the DC power supply and reduce or remove the output voltage until the sensed current falls below the threshold level. The current limiting action is preformed by controlling the conductance of the pass element so that the pass element is always operating within its safe operating area.

Abstract: Stray reactance compensation is provided in a split phase delay equalizer by inserting an auxiliary compensating small reactance in the substantially real arm circuit branch which provides a third order response equal and opposite to the deviation from second to third order in the amplitude response curve caused by stray reactance deviated phase reversal from the ideal.

Abstract: An FM transmitter is disclosed wherein a solid state microwave source at a first frequency is frequency modulated with a baseband signal, and a second such source at a different frequency is frequency modulated with the baseband signal inverted. Each of the modulated carriers is frequency doubled and input to a mixer. The output of the mixer is a carrier, having a frequency which is twice the difference of the two microwave frequencies, and frequency modulated by the baseband signal. An automatic frequency control circuit inputs equal and opposite control voltages to the two microwave sources.

Abstract: An antenna system suitable for airborne use is disclosed. The system is of the type having a blade forming a folded monopole antenna with one terminal serving as a radio frequency input and a second terminal connectable to tuning apparatus. Tuning components switchable to various values are connected at the second terminal. A processor receives the value of a new frequency to be used, computes from stored reference values the values of tuning components calculated to render the antenna in tune at the selected frequency, and commands the switching of the tuning components to the calculated values. A phase discriminator at the first terminal provides the processor with an indication of the extent to which the antenna is in tune at the selected frequency. If it is not in tune, the processor iteratively commands the switching of the tuning components until new values are reached for which the antenna is in tune.