Abstract: A data processing system is disclosed in which memory modules are connected at ports of interconnecting buses, with the physical addresses of the modules not necessarily being contiguous. The system includes a random access memory for translating contiguous logical memory addresses, as generated by a processor, to the physical addresses of the memory modules. The operation of the random access memory is such that memory modules of various sizes can be used together. Switching is provided for selectively interchanging word address bits and module address bits before the transformation is performed by the random access memory, thereby providing interleaving.

Abstract: A communication signal is coupled simultaneously to all three phases of a three-phase power line through a three-phase open delta transformer with the communication signal being applied across the low voltage pair of windings.

Abstract: A clock system is disclosed having two identical clocks not synchronized with each other. Each of the clocks includes a circuit for selecting the output of one of the clocks as the present system output. Further, each clock includes logic for detecting errors in the operation of itself, and of the other. When an error is detected in the operation of the clock selected to be the present system output, a switchover sequence control switches the output signal of the nonselected clock to become the new system output. The switchover sequence control includes a feature which ensures that the interval between pulses in the system output is greater than a predetermined period in order to minimize detrimental effects on circuitry utilizing the clock system output.

Abstract: A radio signal is applied to an in phase detector channel and a quadrature phase detector channel. Each detector channel includes, in cascade arrangement; an in phase downconverter means for downconverting the received radio signal to a baseband signal; a sampling means for sampling the baseband signal at a predetermined rate; and a matched filter means matched to the symbol waveform and wherein the sample pulses are stored over a predetermined period of time that corresponds to two data symbols. The sum of the pulses for the first data symbol and the sum of the pulses for the second data symbol are compared to determine if there has been a phase reversal between the two data symbols. The outputs of the in phase and quadrature phase channels are summed, which results in demodulation of the encoded data.

Abstract: A memory unit is disclosed for receiving and executing instructions transmitted along buses. The memory unit includes registers and control logic that permit it to accept a second instruction from the bus and begin error checking procedures on the second instruction, all while completing the execution of a first instruction.

Abstract: Circuitry for detecting the spectral distribution of a signal that is phase indicative of a digital logic level and providing feedback signals for use in adjusting the amplitude of the signal spectrum to reduce signal distortion toward a value which is substantially identical with the transmitted signal for all points over a given frequency bandwidth. The correction is obtained by applying voltages to variable impedance pin diodes forming part of a series set of tuned filter circuits.

Abstract: A circuit card is disclosed of the type for connection to a system by means of connector pins on the card. The circuit card includes a soft power switch for reducing the power transient effects of inserting the card by gradually coupling the circuit load on the card to the system power supply voltage. Connector pins of various extensions are used to initiate events in the coupling of the circuit load to the power supply voltage. The card further includes logic which causes the circuit load to be gradually decoupled from the power supply upon removal of the card from the system.

Abstract: A processing system is disclosed in which transfers between processors and memory are made on dual redundant buses. In a transfer, the transmitting unit sends the same information simultaneously on each of the buses. The receiving unit makes parity checks on each bus, and compares the information received on one bus with that received on the other bus. The receiving unit includes means for implementing a decision rule, based on these checks and comparison, to choose from which bus to take information, if either.

Abstract: Circuitry for detecting the spectral distribution of a signal that is phase indicative of a digital logic level and providing feedback signals for use in adjusting the signal amplitude of the spectrum to have a substantially zero slope over the relevant frequency bandwith. The correction is obtained by applying voltages to variable impedance pin diodes forming part of a tuned filter circuit.

Abstract: Multiplexed carrier signals modulated with digital data are transmitted through a medium polluted with harmonic signals by asymmetrically positioning the frequency of one of the carrier signals between two of the adjacent system harmonics, modulating that carrier signal with digital data at a baud rate so that the spectral density nulls of the modulated carrier signal in the frequency domain coincide with the two adjacent system harmonics to which spectral distribution the detector response is matched, generating at least one additional carrier signal whose frequency is also positioned between the two same adjacent system harmonics but is different from that of the other carrier signal and whose frequency separation from any adjacent carrier signal is equal to the baud rate or some multiple thereof, and modulating each additional carrier signal with digital data at the same baud rate.

Abstract: The method and apparatus of converting a sine-wave signal of one frequency to a sine-wave signal of a different frequency comprises a four port pass means that is controlled by at least two control signals. An error signal is generated by the difference between the rectified output signal and a locally generated reference signal. The error signal is compared to a high frequency sawtooth signal to provide a pulse width signal which generates a two state output signal. The first state is when the amplitude of the sawtooth signal is less than the error signal and the second state is when the amplitude of the sawtooth signal is greater than the amplitude of the error signal. The two state pulse width modulated signal is combined with the output from a polarity control means for obtaining the control signals.

Abstract: A single sideband signal can be demodulated by using sampled data techniques. An intermediate frequency (IF) radio signal is split into two branches and is sampled by two sample and hold devices; each sample and hold device operates at a rate that is not only a submultiple of the carrier frequency, but is also at least twice the information bandwidth. Prior to, or during sampling of one branch (the quadrature branch), a Hilbert's transform is performed upon the IF signal which results in the output of the two sample and hold devices being in phase quadrature. A phase shift of 90.degree., using a baseband finite impulse response Hilbert's transform filter, is performed upon the output signal of the quadrature branch's sample and hold device. The sum of the inphase sampled signal and the filtered quadrature phase sampled signal produces the demodulated lower sideband while the difference between the two produces the demodulated upper sideband.

Abstract: The present invention uses two interconnected baluns with the balanced output of one feeding a balanced input of the other. When this filter is used in conjunction with a signal frequency converter, the balun pair not only provides extremely effective bandpass filtering so as to pass the RF frequencies and not the IF frequencies but, in addition, provides a condition which appears to the IF as a nearly open circuit and thus provides a large amount of reflection or return of the IF signals to the signal converter. Through the use of additional grounding stubs, additional coupling means, increased separation between coupling means and separated ground planes each singularly or in combination, improved performance has been obtained as compared to the prior art.

Abstract: The present invention is directed to a system which accomplishes forwarding or retransmission of signals requiring preemphasis and signals not requiring preemphasis while using a single spare channel for forwarding either type of signal upon failure of a primary channel. This is accomplished by designing each channel to have passive and selectable circuits through which the signal is passed for preemphasis or attenuation depending upon the type of signal used in the primary portion of that communication channel before being applied to the selection switches of the spare channel.

Abstract: Two identical and interconnected switch matrices are used wherein one is "on-line" and the other is "off-line". If an individual module in the on-line switch fails, an identical module in the standby matrix is switched in to carry traffic. The failed module can then be replaced with an operable unit. The feature of modularity not only greatly enhances the performance of the switch matrix but also provides for quick restoration of the switching apparatus to a preferred configuration of operability.

Abstract: Digital data borne by a carrier signal via a predetermined variation in some characteristic thereof during each baud period with respect to the same characteristic of a reference signal is detected by subdividing each baud period into n intervals, converting the carrier signal characteristic variation to a DC signal which is integrated over a baud period beginning with the inception of each of the intervals and converting to and storing the equivalent data baud value of each integrated DC signal, thus providing multiple messages from which to select a valid message.

Abstract: The phase of the clock timing pulses are continuously optimized relative to the received signal under the control of pseudo-error detectors.

Abstract: A carrier signal bearing digital data which varies a characteristic of the carrier signal during each baud period in a predetermined manner to identify the baud value during the period is demodulated by subdividing each baud period into n intervals, converting the carrier signal characteristic to a DC signal which is integrated over each of the intervals and summing the integrated DC signal attained at the end of each interval with the integrated DC signals attained at the end of the previous n-1 intervals.

Abstract: A clamp circuit that reduces low frequency noise on a wideband signal such as a video signal by more than 50 dB is disclosed and includes an input amplifier for obtaining a difference signal that is the algebraic summation between an input signal having periodically spaced synchronization pulses and a reference signal. The reference signal is generated by sampled data techniques and includes a means for removing the synchronization pulses from the signal. After passing the synchronization pulse through a pulse shaper, they are used to operate a sample and hold device which samples the output of the difference amplifier during the synchronization periods and the sampled output, after being passed through a low-pass filter, is used as the reference signal to the difference amplifier which subtracts the reference signal from the wideband signal. An additional amount of low frequency rejection is provided by passing the difference signal through a switching clamp circuit.

Abstract: Baud timing is derived from an AC signal having n half-cycles during each baud period, for use in demodulating a carrier signal bearing digital information via some predetermined variation in a characteristic of the carrier signal during each baud period, by converting the carrier signal characteristic variation to a DC signal, sampling the DC signal at the same point during each half-cycle of the AC signal, summing the samples corresponding to the same half-cycle of the AC signal within each sequence of AC signal half-cycles occurring over successive baud periods, there being n such sample totals, identifying the largest one of the n totals and sychronizing the baud timing signal to the AC half-cycle corresponding thereto.