Abstract: A first transceiver transmits a set of test levels to a second transceiver as a signal through a communication channel as encoded samples and subjected to one or more of a plurality of line encoding algorithms. An information channel is superimposed in the signal transmitted through the communication channel. The second transceiver determines line encoding with, and conversion between, the companding laws present in the communication channel based on the received set of test signals. The set of test levels are signals having levels determined based on the difference between the normalized amplitude, vertex, or energy curves for the types of companding laws, with or without accounting for other sources of network distortion. Encoded samples representing the transmitted test levels are reconstructed by the second transceiver in accordance with the one or more detected line encoding algorithms, the encoded samples for each of the set of test levels packed into a corresponding sample cell.

Abstract: A method and apparatus are disclosed for reducing the computational complexity of the RSSE technique. The apparatus and associated method does not assume that the signal energy of a pulse that has gone through a channel is always concentrated primarily in the initial taps, as is true for a minimum phase channel. The present invention, however, recognizes that the signal energy is often concentrated in just a few channel coefficients, with the remaining channel coefficients being close to zero. A receiver apparatus and associated method is disclosed for reducing the number of channel coefficients to be processed with a high complexity cancellation algorithm from L to V+K which contain the majority of the signal energy, while processing the L−(K+V) non-selected coefficients with a lower complexity algorithm. By only processing the intersymbol interference caused by a reduced number of channel coefficients (i.e.

Abstract: A first transceiver transmits a set of test levels to a second transceiver through a communication channel in which one or more types of companding laws are used for line encoding. The second transceiver determines line encoding with, and conversion between, the companding laws present in the communication channel based on the received set of test signals. The set of test levels are signals having levels determined based on the difference between the normalized amplitude, vertex, or energy curves for the types of companding laws, with or without accounting for other sources of network distortion. A decision metric is also generated from the difference between the normalized amplitude, vertex, or energy curves for the types of companding laws. The second transceiver then compares a combination of the set of test levels that is received from the communication channel with the decision metric.

Abstract: An iterative decoding system for intersymbol interference (ISI) channels has a module for extracting bit reliabilities from a partial response (PR) channel, an iterative decoder, and a module for updating the bit reliabilities. A transmitter parses a data sequence into blocks that are encoded to generate a sequence of codewords. By encoding, a correlation among the bits of each codeword output to the PR channel is created. A maximum likelihood sequence detector (MLSD) in the receiver produces estimates of transmitted bits from samples of the output from the PR channel. The MLSD detector has a priori knowledge of typical error events that can occur during transmission through the channel. Along with the bit estimates, at each time instant the MLSD detector generates set of error event likelihoods.

Abstract: A counter sequence is mapped with an interleaving algorithm Both the sequence and mapped sequence of values are associated with values in a block of data values and a corresponding block of interleaved values. For a receiver, the mapped counter sequence is employed to generate a sequence of addresses corresponding to of the interleaved block in a buffer. The counter provides a sequence of address values associated with the original sequence of data values before interleaving. Memory addresses for storing the data values in the interleaved block to reconstruct the original block are assigned based on the counter sequence and the mapped counter sequence of values.

Abstract: A first transceiver transmits a set of test levels to a second transceiver through a communication channel with one or more types of companding laws. The second transceiver determines line encoding with, and conversion between, the companding laws present in the communication channel based on the received set of test signals. The set of test levels are signals having levels determined based on the difference between the normalized amplitude, vertex, or energy curves for the types of companding laws, with or without accounting for other sources of network distortion. Additional distortion from line characteristics, such as robbed-bit signaling (RBS) and/or line impairment, may be detected based on changes in encoding sample levels of transmitted test signals that are reconstructed by the second transceiver. The second transceiver may then transmit information to the first transceiver about the companding laws and other sources of distortion present in the network.

Abstract: A method for synchronizing multi-carrier signals in an orthogonal frequency division modulation (OFDM) data transmission system is disclosed which provides maximum likelihood estimation of timing offset and frequency offset. The estimates are able to compensate the estimation error over an entire span of observed data samples. The method requires no training sequence thus enabling blind frequency compensation. The method provides a joint probability density function for the estimates which consists of two terms; one generated from observed data received during a first interval and one generated from observed data received during a second, following, interval. The estimates provided by the method are therefore maximal likelihood over the entire span of observed signals and are a significant improvement over estimates provided by methods based only observations during the first interval. The method is mathematically robust and computationally and statistically efficient.

Abstract: Single-bit-timestamp discrete-rate scheduling distributes service to competing connections (e.g., packet connections such as virtual-circuit connections) using a single bit for each connection, rather than using one or more multi-bit timestamps per connection. Single-bit timestamps are computed and sorted for scheduling packets in, for example, Asynchronous Transfer Mode (ATM) networks, for guaranteeing data transfer rates to data sources and data transfer delays from data sources to destinations. Connections are listed in one of N first-in, first-out (FIFO) rate queues j, each rate queue j, 1≦j≦N, associated with one of N service rates. A scheduler identifies the next connection for service as the connection VCj,i being at the head of the rate queue with the minimum corresponding timestamp among those rate queues having timestamps satisfying an eligibility condition.

Abstract: A system employs a modified Jakes' fading model to generate a fading signal having substantially equivalent autocorrelation values for in-phase (I) and quadrature-phase (Q) components. A Walsh transform may be applied to generate multiple, uncorrelated I and Q components, for multiple fading signals. A complex Rayleigh fading signal according to the modified complex Jakes fading model is provided by a generator having M pairs of I and Q paths. Each pair of I and Q paths includes a corresponding complex carrier generator 201 (M an integer and 1≦n≦M) generating a complex carrier signal with frequency, &ohgr;n, where &ohgr;n is cos ((4n−3&pgr;)/4M). Each of the I paths has a circuit that separates the real component of the corresponding carrier signal to provide a real carrier signal cos (&ohgr;nt). Similarly, each of the Q paths has a circuit that separates the imaginary component of the corresponding complex carrier signal to provide an imaginary carrier signal sin (&ohgr;nt).

Abstract: A circuit performs threshold normalization of accumulated transition probabilities for a given state of a state transition trellis in a maximum likelihood detector. Threshold normalization may be accomplished by comparison and setting of a single bit in stored transition probabilities. Threshold value comparison may be accomplished by comparing the bth bit of the stored transition probabilities if the threshold value is 2b. When all transition probabilities exceed the threshold value at a stage of the trellis, the transition probabilities are scaled, such as by subtracting the threshold value. Scaling may be implemented by setting the compared bth bits to zero before storage. In general, since accumulated transition probabilities are monotonically increasing for transition probabilities of paths through the trellis in both forward and reverse directions, the present invention may be employed for both threshold normalization of both the forward (&agr;) and reverse (&bgr;) transition probabilities.

Abstract: An automatic gain control (AGC) system controls a receiver having multiple amplifier stages with near constant compression. The AGC system controls gain, and thus compression, of each stage employing information generated by the other stages to generate feedback signals at a system level. A central controller uses threshold detection to monitor signal power at each stage of the receiver signal path as well as overall signal gain. Based on these various signal power measurements, the central controller adjusts signal gain of the input to one or more stages, while maintaining overall signal gain for a constant output signal level. The AGC function may be implemented by switching the gain of each stage's variable amplifier in discrete steps in discrete steps, with the step size being coarser for stages closer to the input signal than those closer to the final output baseband signal.

Abstract: An iterative decoder limits the range of extrinsic information used for iterative decoding of an encoded frame of data. The iterative decoder includes two or more separate decoders for decoding a received encoded frame of data. Each decoder employs extrinsic information generated from the soft data generated by another decoder decoding the encoded frame of data. The extrinsic information includes an approximate measure of the probability that a particular transmitted bit received by the iterative decoder is a logic 0 or logic 1. The extrinsic information for the bit originates with one decoder and is used by another decoder as external information about that bit. Implementations of the iterative decoder use saturation values to define the boundaries of the range. The saturation values are selected such that either no or relatively small degradation in BER occurs, and the saturation values also define the width of the binary representation of the extrinsic information.

Abstract: A set of orthogonal sequences (e.g., Hadamard sequences) is decomposed into a set of basis vectors and sets of coefficients, where each set of coefficients represents a particular “vector combination” of the basis vectors that forms one of the orthogonal sequences. Such decomposition of orthogonal sequences into basis vectors and sets of coefficients may allow for a reduction in memory space and/or processing required to generate one or more of the orthogonal sequences during real-time operations of a communications system, such as an IS-95 CDMA system, that employs the orthogonal sequences. In one embodiment, a Hadamard sequence generator includes a controller, a memory, and a combiner. The set of basis vectors are stored in the memory, and each of the Hadamard sequences has a corresponding set of coefficients from which the Hadamard sequence can be derived as a vector combination of the basis vectors.

Abstract: An apparatus and method of a shared correlator system for a code division, multiple access (CDMA) receiver employs scheduling of correlation operations with identification tags (ID-tags). The scheduling allows for shared vector generation and correlation operations between processing units by pipeline processing. The shared correlator schedules correlation operations requested by processing units, generates matched-filter PN vectors associated with the identification tags for the correlation operations, and provides correlation results for the correlation operations. Scheduling may be implemented with a control processor, scheduler and memory. The control processor determines the matched-filter PN vector information for a requested operation using the current state of a reference PN code sequence, and this information is stored as the ID-tag. The control processor stores the ID-tag at an address in memory associated with a slot of a periodic symbol schedule.

Abstract: A product code and interleaving/de-interleaving process are designed to work in combination to improve the coding gain of the product code. Such improvement of coding gain is based on an error constraint. The error constraint is a maximum number of values in error per block in the detected decisions for received output channel samples. The error constraint may be a burst error constraint, such as a maximum number of errors in a block introduced by burst noise in the communication channel; or the error constraint may be an error event constraint, such as the error event generated by an incorrect decision for a path through the trellis of the Viterbi algorithm employed by the detector or a combination of both. In one implementation, a block of data of length N is encoded with a product code of two dimensions with N a positive integer. The product code includes an error correcting capability of detection and correction by a receiver of single one-bit errors in the encoded block.

Abstract: A system for block encoding and block decoding of servo data with a rate (M/N) code, where M is an integer greater than 1 and N is an integer that is greater than M. Two codes are described for the encoding and decoding processes: a rate (2/6) code and a rate (2/8) code. In general, block encoding and-block decoding maps between M servo data bits and N coded symbol bits. Such block encoding with a rate (M/N) code may be employed in a magnetic recording system for encoding servo data that is written to a servo data sector on a magnetic recording medium. Encoded servo data is read from the magnetic medium and block decoded. A forced maximum-likelihood, partial-response (PRML) detector is used to detect the N coded symbol bits from channel samples read from the magnetic medium. Block encoding provides greater coding gain for a detector when the characteristics of the block code are used to improve performance of the PRML detector that is used to detect the N coded symbol bits.

Abstract: A transmit portion of a WB-CDMA transceiver generates one or more spread data streams having values represented by a single bit, allowing for filtering of spread and combined data streams with a root raised cosine (RRC) filter employing single-bit multipliers. The RRC filter is a digital filter that i) employs multiplication of two values in which the length of at least one value is one bit; ii) is preferably implemented with muxs or a simple logic operator; and iii) may employ upsampling and modulation encoding of filter coefficients to reduce the coefficient length to, for example, one bit. The RRC filter may be an FIR filter having either one-bit or multi-bit coefficients, and apply RRC filtering to a spread user stream either before or after the spread user streams are combined. For some implementations, RRC filters are employed to filter each spread user stream prior to combining several processed user steams.

Abstract: An iterative decoder employs detection and post-processing of channel output samples to generate soft output vales for encoded data provided to the decoder for one or more iterations of decoding. The channel output samples account for user data encoded with concatenated codes. For one or more other iterations, the reliability values of the soft values of the prior iteration are updated, generating soft output data for the decoder for the current iteration of decoding. A detector may use a soft-output Viterbi algorithm (SOVA) to detect encoded data from channel output samples, and the SOVA algorithm may be implemented by a Viterbi algorithm generating hard decisions from the output channel samples followed by post-processing to generate and update reliability values for the soft-output values based on the hard decisions and output channel samples.

Abstract: A data transmission system employs an iterative decoder that applies decision feedback equalization (DFE) to channel output samples of a packet of data. The iterative decoder receives a stream of channel output samples as packets that may, for example, be read from a sector of a recording medium. Each packet may represent user data encoded, for example, with a concatenated code formed from N component codes, N a positive integer. The iterative decoder employs I decoding iterations, I a positive integer. DFE employs two filters: a feedforward filter and a feedback filter. The feedforward filter, which may be a whitened-matched filter used for detection, shifts dispersed channel output energy into the current sample. The feedback filter cancels energy of trailing inter-symbol interference from previous symbols.

Abstract: An offset sequence generator generates an offset sequence from a reference sequence, the offset sequence being a cyclic-shifted version of the reference sequence. The reference sequence is a deBruijn sequence formed from a pseudo-noise (PN) sequence augmented with an insert-bit, the insert-bit being inserted at a rollover state of the PN sequence. The offset generator includes a decision circuit that selects values of either the reference sequence or a delayed reference sequence as an input to a mask circuit. The mask circuit applies masks so as to generate the PN sequence of the offset sequence. The decision circuit also detects the rollover state of the PN sequence of the offset sequence, and inserts the insert-bit so as to provide the offset sequence.