Abstract: A device includes a first transistor including a fin and a second transistor including a fin, the fin of the first transistor having a lower charge carrier mobility than the fin of the second transistor. In a method, the fin of the first transistor is treated to have a lower charge carrier mobility than the fin of the second transistor.
Type:
Grant
Filed:
June 18, 2007
Date of Patent:
March 29, 2011
Assignee:
Infineon Technologies AG
Inventors:
Jörg Berthold, Christian Pacha, Klaus von Arnim
Abstract: A component arrangement comprising a carrier, a component in a housing with electrical contacts and a moulding compound that encloses the carrier, the semiconductor component in the housing and the electrical contacts, wherein the component is applied on the carrier, and wherein the carrier is provided with holes, and a method for producing a component arrangement, wherein the carrier is provided with holes, the component is positioned on the carrier, the component is connected to the carrier, the component with the carrier is positioned in the leadframe, and this arrangement is enclosed by a moulding compound.
Type:
Grant
Filed:
September 25, 2007
Date of Patent:
March 22, 2011
Assignee:
Infineon Technologies AG
Inventors:
Michael Bauer, Alfred Haimerl, Angela Kessler, Joachim Mahler, Wolfgang Schober
Abstract: One or more embodiments relate to a semiconductor device, comprising: a inductor coil including a winding; and a capacitor arrangement including at least one capacitor, the capacitor arrangement electrically coupled to the inductor coil, the footprint of the capacitor arrangement at least partially overlapping the footprint of the inductor coil.
Abstract: This application relates to a semiconductor device comprising multiple separate leads molded in a molded structure, and a chip attached to the molded structure over at least two of the multiple separate leads.
Type:
Grant
Filed:
September 26, 2008
Date of Patent:
January 11, 2011
Assignee:
Infineon Technologies AG
Inventors:
Stefan Paulus, Manfred Fries, Martin Petz, Thomas Mueller
Abstract: This application relates to a semiconductor device, the semiconductor device comprising a metal carrier, an insulating foil partially covering the metal carrier, a first chip attached to the metal carrier over the insulating foil, and a second chip attached to the metal carrier over a region not covered by the insulating foil.
Type:
Grant
Filed:
August 5, 2008
Date of Patent:
December 7, 2010
Assignee:
Infineon Technologies AG
Inventors:
Joachim Mahler, Ralf Wombacher, Ralf Otremba
Abstract: This document discusses, among other things, apparatus having at least one CMOS transistor overlying a substrate; and at least one finned bipolar transistor overlying the substrate and methods for making the apparatus.
Abstract: One or more embodiments are related to a semiconductor structure, comprising: a semiconductor chip; a conductive layer comprising at least a first conductive pathway and a second conductive pathway spacedly disposed from the first conductive pathway, the first conductive pathway electrically coupled to the chip, at least a portion of the first conductive pathway disposed outside the lateral boundary of the chip, at least a portion of the second conductive pathway disposed outside the lateral boundary of the chip; and a conductive interconnect disposed outside the lateral boundary of the chip, the conductive interconnect electrically coupling the first conductive pathway to the second conductive pathway.
Type:
Grant
Filed:
September 14, 2007
Date of Patent:
October 19, 2010
Assignee:
Infineon Technologies AG
Inventors:
Helmut Tews, Hans-Gerd Jetten, Hans-Joachim Barth
Abstract: A circuit array includes a plurality cells, wherein each cell has at least one group of odd fins. The cells may be arranged in a repeating pattern that includes mirror images of the pattern. A plurality of fin forming regions are provided about which the fins are formed for the dual fin and single fin transistors.
Abstract: A circuit includes a plurality of first MuGFET devices supported by a substrate and having a first performance level. A plurality of second MuGFET devices is supported by the substrate and have a second performance level. The first and second devices in one embodiment are arranged in separate areas that facilitate different processing of the first and second devices to tailor their performance characteristics. In one embodiment, the circuit is an SRAM having pull down transistors with higher performance.
Abstract: The invention relates to systems and methods for detecting and monitoring tire deformation. In one embodiment, a tire deformation detection system comprises a first electrode, a second electrode, circuitry, and a central control unit. The first electrode is coupled to an interior surface of a tire. The second electrode is coupled to an interior surface of the tire and configured with the first electrode to form a first capacitor. The circuitry is configured to measure a first capacitance of the first capacitor. The central control unit is configured to detect a deformation of the tire based at least in part on the first capacitance.
Abstract: Sigma-delta modulators and a method of modulating are disclosed in which a first sigma-delta modulator having a first quantizer is provided, and a second quantizer is also provided. At least a first node of the first sigma-delta modulator upstream of the first quantizer and a second node of the first sigma-delta modulator upstream of the first quantizer to the second quantizer are coupled together.
Type:
Grant
Filed:
December 22, 2006
Date of Patent:
December 2, 2008
Assignee:
Infineon Technologies AG
Inventors:
Antonio Di Giandomenico, Luis Hernandez, Susana Paton, David San Segundo Bello, Manuel Sanchez-Renedo, Andreas Wiesbauer
Abstract: An amplification apparatus includes an amplifier. The amplification apparatus includes a bias voltage circuitry coupled to the amplifier to provide a bias voltage thereto. The amplification apparatus includes a supply voltage circuitry coupled to the amplifier to provide a supply voltage thereto. The supply voltage circuitry is coupled to the bias voltage circuitry. The bias voltage circuitry is configured to provide the bias voltage depending on the supply voltage.