Abstract: One or more embodiments of the present disclosure relate to a circuit board having a substrate and a plurality of differential signal lines formed on the substrate and transmitting differential signals. The differential signal lines include a first signal line and a second signal line. The first signal line and the second signal line extend along at least two paths that are parallel to each other. The paths of the first signal line and the second signal line switch at path change portions, and the path change portions of neighboring differential signal lines are positioned at different distances away from an edge of the circuit board along the length direction of the differential signal line.

Abstract: A display apparatus with a light-weight power providing unit that can be easily incorporated within an acceptable fastening-error range is disclosed. The display apparatus includes a display panel that displays an image, a backlight assembly that provides the display panel with light, a rear cover that is coupled to the backlight assembly and has a guide unit formed thereon, wherein the guide unit protrudes from a bottom surface of the rear cover by a predetermined height, and a top-receiving container that has an inner space to receive the display panel and the backlight assembly and that is combined with the rear cover. There is also a power providing unit that provides the backlight assembly with driving power. The power providing unit is coupled to the rear cover at a position guided by the guide unit.

Abstract: A liquid crystal display device includes a first substrate which comprises a plurality of pixels where a thin film transistor and a pixel electrode electrically connected to the thin film transistor are formed, the first substrate including a gate line and a data line which insulatingly intersect each other; and a gate driver which applies a gate driving signal to the gate line, the thin film transistor including a gate electrode which is connected to the gate line; a source electrode which is connected to the data line; and a drain electrode which is connected to the pixel electrode, and the pixels being decreased in a value of Cp/(Cp+Clc+Cst) as going toward the gate driver (where, Cp: a sum of parasitic capacity between the gate electrode and the source electrode and parasitic capacity between the gate electrode and the drain electrode, Clc: liquid crystal capacity, and Cst: storage capacity).

Abstract: A display substrate includes a base substrate, a barrier pattern, a source electrode, a drain electrode, a semiconductor layer, an insulating layer, and a gate electrode. The barrier pattern protrudes from the base substrate. The source and gate electrodes are formed adjacent to opposite sides of the barrier pattern on the base substrate. The semiconductor layer is provided on the barrier pattern to connect the source electrode with the drain electrode, and the insulating layer covers the semiconductor layer, the source electrode, and the drain electrode. The gate electrode is provided on the insulating layer, and is overlapped with the semiconductor layer.

Abstract: In a display device, a first frame of input image signals is received by a signal controller, stored in a memory, and applied to rows of pixels while a gate driver scans a gate-on voltage to a gate line in a first mode to select a row of pixels, one row at a time. When a gate driver controller detects that a second frame of image signals is being received by the signal controller, the gate driver controller halts the operation of the gate driver until the second frame of input image signals has all been received by the signal controller and until a scan start signal is detected by the gate driver controller.

Abstract: An improved display substrate is provided to reduce surface defects on insulating layers of organic thin film transistors. Related methods of manufacture are also provided. In one example, a display substrate includes a base, a plurality of data lines, a plurality of gate lines, a pixel defined by the data lines and the gate lines, an organic thin film transistor, and a pixel electrode. The data lines are on the base and are oriented in a first direction. The gate lines are oriented in a second direction that crosses the first direction. The organic thin film transistor includes a source electrode electrically connected to one of the data lines, a gate electrode electrically connected to one of the gate lines, and an organic semiconductor layer. The pixel electrode is disposed in the pixel and electrically connected to the organic thin film transistor. The pixel electrode comprises a transparent oxynitride.

Abstract: To drive light-emitting blocks, currents are sensed through the light-emitting blocks arranged in an M×N matrix (wherein M and N are natural numbers), wherein M rows are connected to a row switching part and N columns are connected to a column switching part. The light-emitting blocks are driven by a local dimming method with feedback control responsive to the sensed currents.

Abstract: Storage of information, such as baseline information and structure ID, in a memory that is mounted on the structure, rather than inside the diagnosis hardware. This allows for faster and more convenient information retrieval. In particular, this approach allows for a more modular system in which different diagnosis hardware or other analyzers can be simply plugged into a structure's sensor network, whereupon they can quickly download any desired structure-specific information (e.g., baseline information, structure ID, and other useful information) from the on-structure memory.

Abstract: A liquid crystal display device for preventing a vertical line defect includes sub-pixels arranged repeatedly in order of red, green, and blue along an N-th (where N is a natural number) horizontal line, and sub-pixels formed in a staggered structure with the N-th horizontal line and arranged repeatedly in order of green, blue, and red along an (N+1)-th horizontal line. Gate lines are formed along the horizontal lines. Data lines are formed to cross the gate lines with a gate insulating layer disposed therebetween and formed to be bent along the sub-pixels of the staggered structure. Thin film transistors are connected to the gate lines and to the data lines and pixel electrodes are connected to the thin film transistors. Storage electrodes overlap the pixel electrodes with the gate insulating layer and a passivation layer disposed therebetween to form storage capacitors.

Abstract: Provided are a circuit board that stores Extended Display Identification Data (EDID) information provided externally and a liquid crystal display (LCD) comprising the same. The liquid crystal display comprises a circuit board and a liquid crystal panel. The circuit board comprises a first connector which receives an externally provided video signal, a second connector which receives an externally provided EDID signal, a memory coupled to the second connector that receives and stores the EDID signal, and a timing controller which receives the video signal from the first connector and generates a video data voltage by using the EDID signal. The liquid crystal panel responds to the video data voltage and displays a video image.

Abstract: An organic light-emitting display device includes a thin film transistor on a substrate, a protective layer and a planarization layer covering the thin film transistor, a pixel electrode connected to the thin film transistor, and a wall positioned on at least a portion of the pixel electrode. The planarization layer includes an aperture which exposes a portion of the pixel electrode. An organic layer is formed on the pixel electrode, and a common electrode is formed on the organic layer. An auxiliary electrode layer is formed to overlap the wall on the common electrode.

Abstract: A liquid crystal display device includes a gate driving shift register having symmetrically split circuit portions by which each of plural gate lines is dually driven from both ends of the gate line during ripple-through scanning of rows of the LCD device. The LCD device includes a timing controller generating an output enable signal and a gate clock, where the timing controller adjusts a timing of a load signal for deciding a data output timing point when data will be loaded into a currently activated display row. The data output timing point is a function of a delay measuring feedback signal that is used to measure the cumulative delays of the sequentially connected stages of the shift register.

Abstract: The present invention provides a shutter pixel, a shutter structure including the shutter pixel, and an exposure apparatus including the shutter structure. The shutter pixel may include a lower substrate, an electrode disposed on the lower substrate, a spacer disposed on the edge of the electrode, a first mirror disposed on the spacer to be separated from the electrode and including a hole, an upper substrate disposed on the lower substrate to face the lower substrate, and a second mirror disposed at the upper substrate and overlapping the hole. Accordingly, a relatively simple structure may be provided.

Abstract: The present invention relates to a method for compensating voltage drop of a display device, a system for voltage drop compensation, and a display device including the same.

Abstract: Disclosed are a display device and a method of driving the same capable of improving display quality and reducing the manufacturing cost. A display device includes a display panel displaying images corresponding to image signals, a light-emission block supplying backlight to the display panel, and a backlight driver outputting a light data signal for determining luminance of backlight. One of a plurality of linear gamma curves is selected from a lookup table in accordance with average image luminance during prescribed frames, and the duty ratio of the light data signal is determined on the basis of the selected linear gamma curve. Each of the linear gamma curves represents the relationship between the average image luminance and the duty ratio of the light data signal.

Abstract: Methods and apparatuses for detecting fastener loosening. Sensors query a structure at a baseline value of an environment variable, such as temperature, and this baseline signal is stored for later use. Subsequently, users can query the structure remotely and at any time, and the signals from these queries are compared to the stored baseline signal. In some embodiments, an index is calculated, and the system determines that one or more fasteners have come loose if the calculated index exceeds a predetermined threshold value. It is desirable to select a time window within which the query signal is most sensitive to fastener loosening but least sensitive to variations in the environment variable. Accordingly, embodiments of the invention include methods and apparatuses for determining an optimal time window for use in calculating the above described index.

Abstract: A display system (110) has a subpixel array (120) and a light source (140). In normal mode, image data (164) are processed by the display system to generate subpixel values (174) for the subpixels (130) and to generate a light source control value (BL) for the light source (140). In bypass mode suitable for testing new types of image-data processing, the subpixel values and the light source control value are generated by an external system (210) and are provided to the display system which is operated in bypass mode. The light source control value is not provided separately from the subpixel values but is encoded into some bits of the subpixel values for compatibility with older interfaces. The light source control value is encoded into the subpixel values' MSBs in case the subpixel values could be truncated. Other features are also provided.

Abstract: A display apparatus including a plurality of gate lines, a data line intersecting the plurality of gate lines; a first pixel unit connected with a n-th gate line of the plurality of gate lines and the data line. A second pixel unit connected with a (n+1)-th gate line of the plurality of gate lines; and a coupling capacitor disposed between the first pixel unit and the second pixel unit, wherein the first pixel unit comprises a first liquid crystal capacitor and a first thin film transistor (TFT), the second pixel unit comprises a second liquid crystal capacitor and a second thin film transistor (TFT), and a source electrode and a drain electrode of the second TFT are connected with both electrodes of the coupling capacitor, respectively.

Abstract: A polysilicon layer including a channel region, and a source region and a drain region located on opposite sides of the channel region is formed on a lower insulating substrate. A gate wire including a plurality of gate lines and a plurality of gate electrodes, which are branched from the gate lines and overlap the channel region, and a storage wire including a plurality of storage electrodes and storage lines connected to the storage electrodes and parallel to the gate lines are formed on the gate insulating layer covering the polysilicon layer. Furthermore, a plurality of first insulating layers covering the gate wire and the storage wire are formed on the gate insulating layers. The first insulating layer has the same shape as the gate insulating layer and is formed extending to the gate wire and the storage wire.

Abstract: A liquid crystal display (LCD) panel includes a substrate, a plurality of parallel control lines on the substrate, and a bonding pad area on the substrate having a plurality of bonding pads therein. A respective one of a plurality of interconnecting conductors connect a respective bonding pad of the bonding pad area to a respective one of the plurality of parallel control lines, each of the plurality of interconnecting conductors having a uniform resistance. According to embodiments of the invention, an interconnecting conductor of the plurality of interconnecting conductors may include a material selected to provide the uniform resistance. The interconnecting conductor may include a first portion including a first material having a first resistivity and a second portion including a second material having a second resistivity different from the first resistivity. The first and second portions may have respective first and second lengths selected to provide the uniform resistance.