Abstract: Extended Universal-Serial-Bus (USB) plugs and sockets are disclosed. The extended USB plug includes an extended pin substrate having an extended substrate length longer than a length of a pin substrate of an industry-standard USB connector plug. There is further included a plurality of USB connector contacts configured to carry USB signals and a plurality of non-USB connector contacts configured to carry non-USB signals. The extended Universal-Serial-Bus (USB) plug, which includes an extended pin substrate having an extended substrate length longer than a length of a pin substrate of an industry-standard USB connector plug. There is included a plurality of USB connector contacts configured to carry USB signals and a plurality of non-USB connector contacts configured to carry non-USB signals.

Abstract: An arrangement for archiving data in a relational database is disclosed. The arrangement includes a first table having a first data field. A value in the first data field is updated by a Relational Database Management System (RDBMS) associated with the relational database when there is a change in the value in the first data field. The arrangement further includes a second table having a second data field represented by a lookup function. The lookup function references the first data field. The lookup function acquiring the value in the first data field for use as a value of the second data field only when a value of the second data field is required by an application program that operates on the relational database.

Abstract: Host computers and peripheral devices communicating through extended USB connectors and plugs are disclosed. The host computer and peripheral device communicate via a non-USB communication mode, using the extended capability of the extended USB connectors and plugs. Software and hardware to facilitate such communication are also disclosed.

Abstract: A software-implemented shared bus system model for modeling a shared bus system that includes a plurality of devices interconnected via a shared bus. The system model includes a first device model for partially modeling a first one of the plurality of devices, the first device model including a first modified logical module and a first modified I/O-specific module. The system model further includes a sharable module having provisioned therein first shareable data. The first shareable data is shareable by the first device model and another device model of the plurality of device models. The first shareable data represents I/O-specific data associated with the first device model that is also needed by the another device model of the plurality of device models during configuration of the shared bus system model.

Abstract: Host computers and peripheral devices communicating through extended USB connectors and plugs are disclosed. The host computer and peripheral device are capable of communicating via multiple communication modes, using the extended capability of the extended USB connectors and plugs. Software and hardware to facilitate such communication are also disclosed.

Abstract: A plug for coupling with an industry-standard EXPRESSCARD™ receptacle is described. The plug includes a plurality of plug-side metal contacts disposed on a bottom substrate. The plurality of plug-side metal contacts is configured to electrically couple with receptacle-side metal contacts in the industry-standard EXPRESSCARD™ receptacle. When the plug is disconnected from the industry-standard EXPRESSCARD™ receptacle, the surfaces of the plurality plug-side metal contacts are exposed by not being covered by a top housing.

Abstract: A method for receiving receive data associated with a bi-directional data flow between a first host computer and a second host computer. The first host computer and the second host computer are coupled via a computer network. The method includes storing receive-facilitating parameters employed for the receiving the receive data in a first control block. The first control block is implemented in the first host computer and associated with the bi-directional data flow. The receiving the receive data is performed in accordance with the TCP protocol. The method also includes employing the receive-facilitating parameters in the first control block to facilitate receiving a given portion of the receive data at the first host computer from the second computer.

Abstract: A clamping ring configured to be coupled to a chamber structure of a plasma processing chamber is disclosed. The clamping ring has a plurality of holes for accommodating a plurality of fasteners. The clamping ring includes a plurality of flanges disposed around an outer periphery of the clamping ring, adjacent flanges of the plurality of flanges being disposed such that a hole of the plurality of holes that is disposed in between the adjacent flanges is about equidistant from the adjacent flanges. The plurality of flanges are configured to mate with the chamber structure. The clamping ring and the flanges are dimensioned such that when the plurality of flanges mate with the chamber structure, recesses between adjacent ones of the plurality of flanges form gaps between the clamping ring and the chamber structure.

Abstract: A plasma processing chamber for processing a substrate to form electronic components thereon is disclosed. The plasma processing chamber includes a plasma-facing component having a plasma-facing surface oriented toward a plasma in the plasma processing chamber during processing of the substrate, the plasma-facing component being electrically isolated from a ground terminal. The plasma processing chamber further includes a grounding arrangement coupled to the plasma-facing component, the grounding arrangement including a first resistance circuit disposed in a first current path between the plasma-facing component and the ground terminal. The grounding arrangement further includes a RF filter arrangement disposed in at least one other current path between the plasma-facing component and the ground terminal, wherein a resistance value of the first resistance circuit is selected to substantially eliminate arcing between the plasma and the plasma-facing component during the processing of the substrate.

Abstract: A method for processing substrate to form a semiconductor device is disclosed. The substrate includes an etch stop layer disposed above a metal layer. The method includes etching through the etch stop layer down to the copper metal layer, using a plasma etch process that utilizes a chlorine-containing etchant source gas, thereby forming etch stop layer openings in the etch stop layer. The etch stop layer includes at least one of a SiN and SiC material. Thereafter, the method includes performing a wet treatment on the substrate using a solution that contains acetic acid (CH3COOH) or acetic acid/ammonium hydroxide (NH4OH) to remove at least some of the copper oxides. Alternatively, the copper oxides may be removed using a H2 plasma. BTA passivation may be optionally performed on the substrate.

Abstract: A method of etching a substrate in a plasma processing system is disclosed. The substrate has a semi-conductor layer, a first barrier layer disposed above the semi-conductor layer, a low-k layer disposed above the first barrier layer, a third hard mask layer disposed above the low-k layer; a second hard mask layer disposed above the third hard mask layer, and a first hard mask layer disposed above the second hard mask layer.

Abstract: A method of efficiently coordinating the communication of data and commands between multiple entities in a system is disclosed. A transaction protocol enabling centralized scheduling of chains of data transfers in a system is disclosed.

Abstract: A network switch includes an input layer to receive a data stream with a set of cells. Each cell includes data and a header to designate a destination device. The input layer includes a set of input layer circuits. A selected input layer circuit of the set of input layer circuits receives the data stream. The selected input layer circuit includes a set of queues corresponding to a set of destination devices. The selected input layer circuit is configured to assign a selected cell from the data stream to a selected queue of the set of queues. The selected queue corresponds to a selected destination device specified by the header of the selected cell. An intermediate layer includes a set of intermediate layer circuits, each intermediate layer circuit has a set of buffers corresponding to the set of destination devices.

Abstract: The invention provides a dynamic domino circuit that is robust under noisy condition. The invention also provides a dynamic adder that contains nodes that can produce true dynamic inversion without compromising area or speed. The invention further improves speed of the adders by cutting the latch delay while not requiring complex clocking.

Abstract: The present invention provides for a method and system for verifying hardware operation of an Application Specific Integrated Circuit (“ASIC”) chip. The ASIC includes microcode logic for enabling Transmission Control Protocol/Internet Protocol (“TCP/IP”) processing. The method is performed in a system that includes a first computing device having a processor and computer code for simulating a computing device that includes the ASIC. Wherein the ASIC is tested against a conventional TCP/IP stack included in a second computing device coupled to the first computing device.

Abstract: A method of determining a parameter of interest during fabrication of a patterned substrate includes illuminating at least a portion of the patterned substrate with a normal incident light beam, obtaining a measured net reflectance spectrum of the portion of the patterned substrate from a normal reflected light beam, calculating a modeled net reflectance spectrum of the portion of the patterned substrate, and determining a set of parameters that provides a close match between the measured net reflectance spectrum and the modeled net reflectance spectrum. The modeled net reflectance spectrum is calculated as a weighted incoherent sum of reflectances from n?1 different regions constituting the portion of the patterned substrate, wherein the reflectance of each of the n different regions is a weighted coherent sum of reflected fields from k?1 laterally-distinct areas constituting the region.

Abstract: The present invention provides for a method and protocol for high bandwidth, low-latency and reliable transfer of variable length FC Frames over the Gigabit Ethernet.

Abstract: A data optimization engine for optimizing selected frames of a first stream of data. The data optimization engine includes a transmit interface circuit coupled to an optimization processor, the transmit interface circuit being configured for receiving the first stream of data. The transmit interface circuit includes a traffic controller circuit for separating frames in the first stream of data into a first optimizable frame and a first non-optimizable frame, and an optimization front-end circuit coupled to the traffic controller circuit to receive at least a first portion of the first optimizable frame. The optimization front-end circuit includes a protocol conversion circuit configured to convert data in the first portion of the first optimizable frame from a first protocol to a second protocol suitable for processing by the optimization processor, the first protocol specifies a first word length, the second protocol specifies a second word length different from the first word length.

Abstract: The invention provides a water supplying apparatus and method thereof which has a high capacity of peeling and removing a disused material such as a resist film and the like, and can efficiently use water vapor. A water supplying apparatus for executing a washing process, a cleaning process and a working process of a subject, is provided with a water vapor body supplying means for supplying a water vapor body, and a water mist body supplying means for supplying a water mist body containing liquid water fine particles, and the structure is made such that said water vapor body and said water mist body are supplied to the subject by independently controlling said two means.

Abstract: An integrated circuit configured to capture an input signal to produce an output signal. The input signal is synchronized with a first clock signal. The output signal is synchronized with a second clock signal having a second frequency different from a first frequency associated with the first signal. The integrated circuit includes a first clock domain gating circuit having a first output terminal and a first input terminal. The first clock domain gating circuit is configured to be clocked by the first clock. The first input terminal is coupled to receive the input signal, and the first clock domain gating circuit is configured to toggle a state of a signal on the first output terminal from one of a first state and a second state to the other of the first state and the second state every time a pulse is detected in the input signal, thereby producing a latched output at the first output terminal.