Abstract: A hard disk drive that determines a flying height from a slope of a line created from a ratio of amplitudes of frequencies in response to impulse functions. A first set of amplitudes of reference frequencies can be determined from a reference impulse. A second set of amplitudes of data frequencies can be determined from a data impulse during operation of the disk drive. Ratios of amplitudes of the data and reference frequencies at different discrete frequencies can be plotted. The slope of the plotted line corresponds to the difference between the flying height when the reference impulse is generated and the flying height when the data impulse is generated. The disk drive may utilize the slope in a feedback routine to control the flying height.

Abstract: A platform that includes a vibration sensor located within an inner core of a table. The table may have a first plate that supports a vibration-sensitive payload. The first plate may be separated from a second plate by the inner core. The sensor can be located within the core directly below the device. The sensor can be connected to an electrical connector attached to an external surface of the table. A monitor can be readily plugged into the electrical connector to obtain vibration data from the sensor. The platform may also include a damper located within the inner core to reduce vibration of the table. The damper may be an active device that is connected to control circuits located within, or outside, the inner core.

Abstract: The invention accepts user input that describes the circuit elements of a digital circuit and the interconnections between those elements. Based upon the user input, the invention computes the maximum setup and hold times for each data input of the integrated circuit. First, maximum and minimum delays from the clock inputs to the storage elements on the integrated circuit. Similarly, the maximum and minimum delays from the data inputs of the integrated circuit to each level one storage element are determined where a level one storage element is defined as a storage element that has no other storage elements interposed between it and a data input. For each data input/level one storage element pair, the setup time is computed based upon the previously calculated maximum data delay and minimum clock delay and the required setup time for the element. The desired setup time for a data input is the maximum setup time over all the level one storage elements coupled to that data input.

Abstract: A method and apparatus for automatically focusing cameras. An auto focus circuit detects highly bright objects contained within an image frame of a scene. If highly bright objects are not detected, an auto focus processor adjusts the focus of the camera to maximize high spatial frequency components of the image frame. The auto focus processor focuses on the highly bright objects by minimizing a count function that indicates the number of pixels having greater magnitude than a threshold reference.

Abstract: The method and apparatus of the present invention provides an interface between a testing device and a random access memory (RAM). The RAM comprises two types of RAM, a TAG RAM and a data RAM. In normal operation, the TAG RAM is not coupled to any devices external to the RAM. Thus, to test the TAG RAM, means must be provided to couple the testing device with the RAG RAM. One possible configuration for interface the TAG RAM with the testing device is to dedicate a line from the testing device to the TAG RAM for each output pin of the testing device, which significantly increases the size of the chip. To reduce this increase in size, according to the present invention, the write lines from the testing device share the bus used by the TAG RAM during normal operation. A multiplexer selects between the testing data and normal address data to insure the integrity of data over the bus.

Abstract: A random access audio/video processor having multiple outputs is disclosed. The processor includes a main control unit with analog video and audio back panels, an analog input/output board, audio and video processing boards, video effects board, synchronization board, and a system board (containing the main CPU). The video processing board includes a compressor for compressing input video signals, and triple transfer buffers for intermediate storage of digital video path. The video processing board further includes decompression circuits coupled to each of two triple transfer buffers for decompressing compressed stored video, and providing the decompressed video channels to an effects board for the addition of special effects. The audio processing board contains processors for compression, decompression, and effects, as well as triple transfer buffers. The triple transfer buffers include present, past, and future buffers which jointly operate to minimize discontinuities in the output channels.

Abstract: An apparatus and method for converting an input data character stream into a variable length encoded data stream in a data compression system. A sliding window data compression algorithm is combined with Huffman encoding on the strings and raw bytes. The Huffman table, in a compressed form, is prepended to the encoded output data. The Huffman codes representing the shortest strings encode both the string length and part of the string offset. Assigning Huffman codes to represent the combined length and offset allows the use of a smaller sliding window size without sacrificing compression ratio. The smaller window size allows implementations in software and hardware to minimize memory usage, thus reducing cost.

Abstract: The charge shared precharge circuit of the present invention is coupled to the match line. The precharge circuit is disposed between the match line and a match line, and includes a CMOS passgate having an N channel and a P channel gate. An inverter acts as a match driver and is coupled between the match and match lines at the CMOS passgate's input and output. The input to the N channel gate of the pass gate is coupled through an inverter to the input of the P channel gate. The N channel gate is further coupled to V.sub.cc through two serially coupled P channel transistors receive BEQ line and an SAE signal, respectively. At the beginning of a compare cycle, BEQ is driven low as is SAE, thereby turning on the serially coupled P channel transistors and coupling V.sub.cc to the input of the N channel gate of the passgate. The P channel gate of the passgate is also opened due to the placement of the inverter between the N and P channel gates.

Abstract: A stand for supporting an elongate object such as a Christmas tree in a substantially vertical orientation has a central tubular support (4) adapted to receive an end of the object, and a plurality of legs (12) releasably securable on the tubular support (4) so as to extend substantially radially therefrom, including lugs (20) which engage in slots (21) in the support to provide releasable fixing of each leg to the central support (4) at a first point on each leg, and a locking collar (10) which is slidably disposed on the support (4) securably overlying lugs (24) to engage each of the legs (12) at a second point thereon.

Abstract: A graphical user interface for displaying and selecting video programs, such as video on demand, includes a video on demand server coupled to a communication medium. A plurality of settop box receivers are coupled to the communication medium for receiving digitized programming in the form of movies and the like from the video on demand server. The settop box includes a central processing unit (CPU) coupled to a memory and other electronic modules. The CPU generates and displays the graphical user interface on the subscriber's television. The graphical user interface is based upon a metaphor in which a world of spaces are organized as part of a studio back lot through which a user may navigate. The back lot includes a Poster wall which presents to the user a series of movie posters representing available selections.

Abstract: Simple and efficient electronic circuits and methods are disclosed for better use of parallel optical interconnect system transmitting a plurality of dc NRZ data and an independent clock signal. The present invention dynamically compensates for the effects of the substrate temperature and aging behavior of the light emitters at both the transmitter and the receiver. In addition, a special arrangement of light emitters is used to reduce or avoid skew problems.

Abstract: Full-motion animation video is displayed in a computer system through use of sprite objects. The sprite objects define the images on the output display, and the locations of the sprite objects are changed to create the animation. The computer system includes three areas of physical memory assigned the status of a front buffer, a back buffer, and a cache buffer. The front buffer stores a frame currently displayed on the output display. The cache buffer is utilized to store a subset of the sprite objects so that all sprite objects need not be rendered for each frame of animation. The contents of the cache buffer are copied to the back buffer during display of the front buffer. To display a subsequent frame, the front and back buffers are switched. A cache buffer permits display of full-motion animation by minimizing use of processor and computer resources.

Abstract: A state machine synthesis tool, a state table script generator, a state table extraction tool, a simulation driver, a simulator, and an interactive reporter, are provided to verify the design and implementation of finite state machines (FSMs). The synthesis tool takes a formal specification of a logic circuit where FSMs are embedded as input, and generates a gate level specification of the logic circuit. The state table script generator takes the same formal specification of the logic circuit as input, and generates state table extraction command files for the FSMs. The state table extraction tool takes the gate level specification of the logic circuit and the state table extraction command files of the FSMs as inputs, and generates state tables for the FSMs.

Abstract: The present invention discloses apparatus and methods for comparing the contents of two digital words and determining whether or not they identically match. The present invention's high speed compare circuit includes a plurality of bit compare block circuits (0 through N) which are coupled in a wired OR configuration to a match line. Each of the bit compare blocks receives a single bit from a first word A to be compared to a corresponding bit in a second word B. A charge share precharge circuit is coupled to the match line for precharging the match line to a voltage level of V.sub.cc /2. A match feed back circuit is also coupled to the match line and the charge precharge circuit to improve the speed at which the match line is precharged to the voltage level of V.sub.cc /2. A latch is coupled to the match line to electrically latch the state of the match line subsequent to the comparison operation.

Abstract: A method and apparatus for quickly copying a first frame region into a second frame region. A video memory array comprising a plurality of video random access memory devices is divided into at least two frame regions. A background image is rendered by a central processing unit into a background frame region within the video memory array. The central processing unit then requests the background image in the background frame region to be copied into a new frame region in the video memory array. A dedicated circuit copies the entire background image in the background frame region into the new frame region. The dedicated circuit operates by using a serial data register within each video random access memory device during the vertical retrace period of a video timing signal. The dedicated circuit performs the background frame copy without requiring any processing resources from the central processing unit.

Abstract: A random access audio/video processor having multiple outputs is disclosed. The random access audio/video processor includes a main control unit having an analog video back panel, an analog audio back panel, an analog input/output (I/O) board. An audio processing board, a video processing board, a video effects board, a syncronization board, and a system board (containing the main CPU). The video processing board includes a compressor for compressing input video signals, and a triple transfer buffer, for intermediate storage of digital video path. The video processing board further includes decompression circuits coupled to each of two triple transfer buffers for decompressing compressed stored video, and providing the decompressed video channels to an effects board for the addition of special effects. The audio processing board contains four digital signal processors for audio compression, decompression, and effects processor.

Abstract: A hand gun is completely concealed within a gun carrying pack. The pack is mounted on a wearer by a belt around the wearer's waist. The pack has a pouch, concealed behind an additional belt strap and clip, for carrying a hand gun. The pouch has front and rear walls. The front wall is permanently attached to the rear wall at the bottom and on one side, but releasably attached by two zippers located on a zipper track at the top and on the other side. The pouch completely conceals a hand gun carried within the pouch. The additional belt strap and clip are connected across the zipper track at the top corner between the releasably attached top and side. By unclipping the additional belt strap and clip, a wearer can pull open the zippers to open the pouch to access the hand gun carried within.

Abstract: An apparatus and method are disclosed for converting an input data character stream into a variable length encoded data stream in a data compression system. The data compression system includes a history array. The history array has a plurality of entries and each entry of the history array is for storing a portion of the input data stream. The method for converting the input data character stream includes the following steps. Performing a search in a history array for the longest data string which matches the input data string. If the matching data string is found within the history buffer, the next step includes encoding the longest matching data string found by appending to the encoded data stream a tag indicating the longest matching data string was found and a string substitution code.

Abstract: The method of the present invention achieves a desired assignment of the physical cell slots comprising a time division multiplexed frame to embedded channels by ascribing an element address to uniquely identify each of the cell slots of the frame. A logical assignment of the cell slots of the frame is made to the embedded channels to be established between one or more specific data sources and sinks. A transform chosen to produce a particular distribution of assignments is then applied to the set of element addresses to produce a set of cell slot addresses, each of which uniquely identifies each cell slot of the frame by its relative physical position within the frame. Each of the element addresses (used to logically associate a cell slot with a channel to be established) is uniquely linked on a one-to-one basis with one of the set of cell slot addresses (used to identify relative position of a cell slot within the frame) through the predetermined transform.