Abstract: A communications system (30) includes a transceiver (42) for transmitting a plurality of bins. Individual bin BERs (bit-error-rates) are iteratively equalized. This is accomplished by applying a fine gains adjustment to the transmit power of the transceiver (42). Specifically, the BER of the bins is equalized by calculating an adjustment gain and subtracting the adjustment gain from the bin currently having the maximum margin and adding the same adjustment gain to the bin currently having the minimum margin. The iterations continue until all of the bin margins are within a predetermined threshold. This changes the individual bin transmit power levels without substantially changing the aggregate transmit power level. The BER is substantially equalized, without causing the individual transmit power levels to exceed a predetermined range, such as that required by ANSI T1E1.4.

Abstract: A method of characterizing dynamics of a workpiece handling system includes providing a workpiece or substrate (14), supporting the substrate (14) with a workpiece handler (13), providing a motion for the workpiece handler (13), transforming the motion into a signal, converting the electrical signal into a measurement of distance, and using the measurement of distance to determine a vibration in the motion.

Abstract: A waveform shaping circuit (120) provides a shaped variable pulse width modulation signal (VPWM) for an SAE (Society of Automotive Engineers) J1850 compliant bus. The J1850 specification defines a single wire multiplexed bus protocol for an automotive application. A counter logic circuit (440) receives a variable pulse width modulation signal (VPWM) signal having unshaped rising and falling edges and a clock having a period smaller than a desired rise or fall time. The counter logic circuit (440) shapes the rising and falling edges of the VPWM signal by sequentially switching each of a variable weighted resistor string (410) to produce an unfiltered shaped VPWM signal. The unfiltered shaped VPWM signal is smoothed by a low pass filter (430) to produce a smoothed shaped VPWM signal.

Abstract: A native microprocessor (20) accesses a foreign block of computer code. An initial block scope defining translation parameters is assigned to the block (106). The block of "foreign" code is translated to "native" code (108). An optimization efficiency is calculated for the translated block (110). A rescheduling criterion is established based on the optimization efficiency (112). The block of native code is executed (114). On subsequent accesses of the block when the reschedule criterion is met (116) the block scope is redefined (118).

Abstract: A mold tool (40) includes a lower platen (10) and an upper platen (18) which have modified surfaces (16) and (20), respectively. The modified surfaces are formed by implanting an implant species (14) at least into areas of the platens which will be in contact with a molding compound resin. By modifying the surface of the molding tool by ion implantation, the need for cleaning the mold tool is reduced due to lower surface friction and wettability of the modified surfaces. These surface characteristics also facilitate easier release of the molded package from the tool. At the same time, wear resistance of the mold tool is improved due to increased surface hardness.

Abstract: An on-chip optimization circuitry (105) of a semiconductor device (100) provides a delay value to a delay generator (120) indicating an amount to delay an active signal edge. Based on the delay value, a modified device timing is created. Using the modified device timing, a portion of the semiconductor device (130) is tested using on-chip verification circuitry (110) to determine functionality. Based on functionality, a determination is made whether an optimal delay value has been found (550). If an optimal delay value has not been determined, a new delay value is used to produce a new modified device timing (516) and the sequence of testing and determining functionality is repeated until a optimized value has been determined.

Abstract: A capacitor (200) having an actual physical capacitance value of Cact and is coupled to an oscillator (36). The oscillation frequency of the oscillator (36) can be changed by changing the effective capacitance of the capacitor (200). The actual capacitance (Cact) of capacitor (200) can be altered to appear to be any effective capacitance (Ceff) between zero and a value much greater than Cact by using a Miller effect. In order to alter the effective capacitance of the capacitor (200), a representation of the output osculation signal (16) is provided to a frequency adjust stage (22). The frequency adjust stage either passed the signal (16) with 0.degree. phase shift or with 180.degree. phase shift. In addition to shifting the phase, the stage (22) will amplify or attenuate the signal (16) to result in the phase shifted and amplified/attenuated frequency adjusting signal (24).

Abstract: A method for chemical/mechanical polishing (CMP) uses a slurry (22). This slurry (22) contains one or more ammonium salts, such as ammonium nitride (NH.sub.4 NO.sub.3), as an oxidizing/etching species within the slurry (22). This slurry (22) is used to polish a metal layer (14) whereby the ammonium salt does not create slurry distribution problems, does not contain metallic species, does not contain mobile ions like potassium, and is environmentally safe.

Abstract: The present invention determines whether two design files have identical functionality by attempting to create a binary decision diagram (BDD) for corresponding verification output pairs(302). When the BDD creations are not successful for all evaluated output pairs a set of cutpoint pair candidates are identified(303). An automatic test program generator (ATPG) is used to determine whether or not the cutpoint pair candidates are invalid cutpoints(304). The invalid cutpoints are removed from the set of cutpoint pair candidates(305). A cutpoint pair candidate having known support is selected(306). An exclusive-or of the outputs of the selected candidate is formed (307). A BDD for the resulting XOR function is attempted (308). If a BDD having a zero or one value is built then the selected candidate is valid indicating equivalence (310). If the BDD is neither the zero function nor the one function, the cutpoint pair is invalid if all of its inputs are verification inputs (311).

Abstract: A non-linear charge pump (1120) provides various voltages for use in a nonvolatile memory (400) and operates at low power supply voltages. The non-linear charge pump (1120) includes at least two non-linear voltage doubling stages (1132, 1134), which allows a capacitor formed with relatively thin gate oxide in a first stage (1132) to be made larger than a capacitor formed using relatively thick gate oxide in a second stage (1134). An output of a last voltage doubling stage (1136) is then input to a linear stage (1150) to generate a precise voltage. Another charge pump (1140) including non-linear stages (1142, 1144) followed by a linear stage (1146) is used to generate a reference voltage for the main non-linear charge pump (1130). The nonlinear stage (1130) includes a special bulk biasing circuit to bias the bulk of a transistor (1285) on the output side of the charging circuit (1284, 1285, 1286, 1287) continuously to prevent forward biasing the parasitic drain-bulk diode.

Abstract: An asynchronous digital mixer (20) receives digitally sampled audio signal data at different unrelated asynchronous sampling rates. The audio data is then edge synchronized and mixed using a summing element (28) and an oversampled sigma delta digital modulator (42), where a single bit output of the digital modulator (42) can be output as an analog signal with the use of a smoothing filter (46), or further decimated using a digital decimation filter (44) for storage on a digital media. Additionally, analog audio signals can be converted and mixed digitally within the system using an analog interface (35) without having to decimate and filter each analog input signal individually.

Abstract: An apparatus (900) for performing the steps of data compression and data expansion. Where the steps of compression of use a modulo arithmetic unit (915) for identifying matching blocks of data that are offset from each other by a multiple of N. A matching block of data is compressed by the apparatus (900) by replacing it with an escape sequence representing the size and offset of the matching block of data. The apparatus (900) identifies a least used data value for use as an escape character to identify the escape sequence. The apparatus (900) performs data expansion by identifying escape sequences and locating an expanded block of data that matches the data represented by the escape sequence by multiplying the offset represented in the escape character by N to specify the offset to the expanded block of data.

Abstract: A memory (400) includes a sense amplifier (500) formed with current-to-voltage converters (512, 513) connected to multiple bit lines, with a common current source (548) forming a current reference, and a common latching comparator (530). A column decode select circuit (515) which selects one of the multiple bit lines is interposed between the current-to-voltage converters (512, 513) and an input of the latching comparator (530). The distribution of the components of the sense amplifier (500) allows operation at low power supply voltages. The sense amplifier (500) uses a clamp and a loading device to establish a first discharge rate on a reference input of the latching comparator (530). The state of the selected memory cell establishes a second discharge rate on another input of the latching comparator (530), which is greater or less than the first discharge rate depending on the state of the memory cell. Portions of the comparator (530) also double as latches during a program mode.

Abstract: A control gate driver circuit (900) provides a variety of voltages to a control gate (21) of a floating gate nonvolatile memory cell (10) using a single circuit. During a read mode, a bias circuit (920) and a reference transistor (925) bias a pass transistor (936) connected to the output of a level shifter (910) to be slightly conductive and thus biases control gates without the need for a charge pump. During programming, a pulse circuit (940) gradually builds the program voltage provided to cells along a selected row, allowing the use of smaller pass transistors (932, 934) and smaller capacitors in the charge pump of the supply (930). Cells in an unselected row are driven to a different voltage, decreasing junction leakage and maintaining high disturb voltage in cells in the unselected row. The control gate driver circuit (900) is implemented using only P-channel pass transistors, eliminating the need for a costly triple-well process.

Abstract: Generation of an output voltage (28) greater than that of a reference voltage (20) is accomplished using a self starting low voltage charge pump (10). A start-up clock circuit (12) comprising a ring oscillator (40) is used to generate a ting oscillator clock signal (63) which can be used allow the charge pump (10) to begin operation before an external clock signal (44) is available.

Abstract: An integrated circuit memory (10) has a redundant column (20) located approximately in the middle a memory array (80, 81). Input/output (I/O) blocks (49, 70) are located on a periphery of the memory (10). A redundant multiplexer (24) is coupled to the redundant column (20) and to a top redundant global data line (36) and a bottom redundant global data line (34). Data is routed between the redundant columns (20) and the I/O blocks (49, 70) via the top and bottom redundant global data lines (36, 34) to effectively shorten the redundant global data line, thereby reducing the amount of redundant data line load capacitance. A fuse circuit (50) is used to program which of the top or bottom global data lines (36, 34) replaces a defective data path. This arrangement permits increased redundant array efficiency while achieving the required performance goals.

Abstract: A security system for a data processor. The data processor includes a register storage area (14) and a main memory storage area (16). The register storage area (14) and the main memory storage areas (16) are defined to assure that as a voltage is varied, that the integrity of the register storage area (14) is guaranteed longer than the integrity of the main memory storage area (16).

Abstract: A method and circuit for determining correspondences between storage elements of a first circuit model and storage elements of a second circuit model. A first circuit model is received (102) and a second circuit model is received (104). Next, input correspondences (106) and output correspondences (108) between the circuit models are received. Each of the circuit models include a plurality of inputs, a plurality of outputs, a plurality of storage elements, and a plurality of logic functions. Signatures of each uncorresponded storage elements in the first circuit model (110) and the second circuit model (112) are determined. The signatures of the storage elements are compared (114). When a signature of a storage element of the first circuit model compares favorably to a signature of a storage element of the second circuit model, a correspondence is determined between the respective storage elements (116). Compatible cluster analysis may also be used in the method.

Abstract: The output frequency (14) of an oscillator circuit (10) can be controlled by replacing at least one of the reactive components (40), such as a capacitor or inductor, with a synthesized element (22). The synthesized element creates a signal that corresponds to the response of the reactive component it is replacing. The synthesized element may be a current source (44), such as a field effect transistor, that is capable of operating at low voltages.