Abstract: Cache memory having pseudo virtual addressing, in which the addressing is performed by using the "offset" field of a current address and a physical address field of an address previously used and stored in a first register, and where, for each logical current address a comparison is made between the logical page addresses of the current address and that of the last used physical address which is stored in a second register. Along with the requested information the cache memory outputs, if available, the effective physical page address of the information, which is compared with the physical page address used for addressing and stored in the first register. In this way, the addressing is performed by physical addresses but without need to wait for translation of a virtual/logical address into a physical address.

Abstract: In a computer system having a hardware and/or firmware design problem which causes a false boundary error under certain conditions, the subject method serves to handle and correct the false boundary error condition in the operating system. This recovery process is carried out such that the information from which the faulting address was developed is redistributed among a plurality of information components in such a manner that the false boundary error will not recur on retry. Thus, the process masks the problem by remapping the virtual address components of the faulting instruction so that the final virtual address, though identical to the failing one, is processed without fault by the central processor unit during recovery.

Abstract: A memory controller in which a number of local memories are primarily dedicated to the shared use of a number of local processors of a data processing system to increase the efficiency of use of both the processors and memories. A controller is associated with each local memory to control connection of any one of the local processors to its associated local memory. A local processor can also be connected via a controller and an adapter circuit connected to the controller to a system bus to obtain access to circuits connected thereto. In addition, a system processor connected to the system bus may also be connected to any particular one of the local memories via its associated controller and adapter connected thereto to load data or programs into the local memory for use by the local processors, and to read out the results of previous processing done by the local processors.

Abstract: In order to determine if a micropackage containing a plurality of integrated circuits, at least some of which are supplied with a reference voltage, should be classified as "risky" the reference voltage current is measured for each micropackage in a group of logically identical micropackages. The measurements are arranged for statistical analysis, and an initial threshold is selected above which a micropackage is classified as "risky". The subsequent history in operation of measured micropackages, as well as reference voltage measurements on additional newly fabricated like micropackages, is entered into the database to permit refining the position of the threshold. In one variant, all micropackages in an initially measured group are "passed".

Abstract: A computer aided software engineering tool is disclosed which is particularly well adapted to identify potential Assembly language source code errors resulting from the analysis of statements which do not contain incorrect syntax, limits, operand specification, etc.; i.e., do not contain any errors of the type which can be generally categorized as incorrect usage. This objective is achieved by providing a debugging program which has a complete awareness of the specific machine architecture, such as the function of each instruction and the register(s), flags, etc. it affects.

Abstract: A compiler module is disclosed which minimizes pipeline breaks by reordering object code instructions to avoid conflicts between closely grouped instructions to the extent possible. Representation of each object code instruction in a small sequential group is temporarily held in a buffer and is assigned a pair of Attribute Words. Potential conflicts which a newly called instruction may have with those instructions already in the buffer are ascertained by logically AND-ing its Attribute Word with those of the other instructions and examining the result. If a conflict does exist, an attempt is made to resolve it by determining if the conflicting instruction already in the buffer can be moved ahead of one or more other instructions in the buffer such that the conflict is eliminated or minimized. This procedure involves a comparison of the Attribute Words of the candidate instruction to be moved, I.sub.m, with the other instructions in the buffer.

Abstract: A local memory fast selection apparatus is utilized in a data processing system having a plurality of memory resources including a local memory and addressing by logical/virtual addresses which are converted into physical addresses. The local memory fast selection apparatus comprises a memory management unit (MMU) for converting a logical address in a physical address and for generating a destination code which identifies the memory resource, and an auxiliary memory having the same number of addressable locations of the MMU and loaded together with the MMU. The auxiliary memory has a physical address corresponding to the logical address by which the MMU is addressed and a destination code. The auxiliary memory stores a bit decoded from the destination code and selects a predetermined memory resource.

Abstract: In a data processing system which employs a cache memory feature, a method and exemplary special purpose apparatus for practicing the method are disclosed to lower the cache miss ratio for called operands. Recent cache misses are stored in a first in, first out miss stack, and the stored addresses are searched for displacement patterns thereamong. Any detected pattern is then employed to predict a succeeding cache miss by prefetching from main memory the signal identified by the predictive address. The apparatus for performing this task is preferably hard wired for speed purposes and includes subtraction circuits for evaluating variously displaced addresses in the miss stack and comparator circuits for determining if the outputs from at least two subtraction circuits are the same indicating a pattern yielding information which can be combined with an address in the stack to develop a predictive address.

Abstract: Apparatus for automatically adjusting the distance of a printing head from a printing support wherein motor means enable changing, on command, the print head distance from the support and a movable armature/plunger electromagnetic detector, fixed to the printing head is energized, when the print head is moved far from the printing support, so as to perform the cocking of the armature/plunger and is thereafter maintained in energized status by a minimal current for holding the electromagnet in cocked state, so that a subsequent movement of the print head towards the printing support, owing to the interference with the printing support of an actuation element coupled to the armature/plunger, causes armature/plunger release and a reluctance change, hence an e.m.f. induced in the energization winding which is detected by a comparator circuit and signaled to a control logic to indicate that the print head is at a predetermined distance from the printing support.

Abstract: Spurious cavity resonance effects in a cabinet housing electronics circuitry are suppressed by determining the maximum repetition rate or frequency for legitimate signals which can appear in the circuitry and then establishing the dimensions of each cavity within the cabinet such that each cavity's resonant frequency is higher than the critical repetition rate/frequency. Since a given cavity in a cabinet is typically block-shaped (such as the space between a cabinet door and the circuit panel facing the door), a special purpose formula may be employed to obtain a good approximation of the cavity's resonant frequency, and the cavity dimensions then adjusted to raise the cavity resonant frequency above the critical frequency. For the still more particular cavity configuration in which the length is greater than the width which is much greater than the depth, a further simplified formula can be employed to find an approximate cavity resonant frequency.

Abstract: A memory system includes a plurality of memory modules, wherein the selection of one among the memory modules is performed in preselection as to the memory activation for a memory access operation on the basis of the previously performed selection of the same module for a preceding memory access operation and wherein, in case the performed preselection is not the appropriate one, the appropriate selection is first performed and then the memory access operation is "retried".

Abstract: An automatic paper bail actuator for a printer having a rotating platen or equivalent means for feeding a printing support including a helicoidal spring wound on the platen shaft and having two end arms, a first arm being elongated to interfere with the bail and a first reference stop, the spring coil being clamped on the shaft by interference with the bail and opening the bail when the shaft rotates in the direction opposite to the one providing normal forward feeding of a printing support, closing the bail when the shaft rotates in the direction providing normal forward feeding until the first arm interferes with the first reference stop and releases the spring coils; the second arm interfering with a second reference stop for a rotation of the shaft in the direction opposite to the normal one and releasing the spring coils for a predetermined angular position of the spring and the first arm, hence for a predetermined open position of the bail.

Abstract: A data processing system having a dual arbiter for controlling access to a system bus where two processors, each clocked by one of two timing signals having equal periods but out of phase by half a period, operate synchronously each to the other, but outphased by the half period of the clock signal, and generate equal priority signals requesting access to a system bus, each processor in a time distinct and non overlapped phase of the respective timing signals, and where an arbitration unit grants system bus access to either one or the other requesting processor on the time order in which the access requesting signals are received, the granting being performed asynchronously and without sampling and set up delays.

Abstract: A computer aided software engineering tool is disclosed which is particularly well adapted to identify potential Assembly language source code errors resulting from incorrectly used symbolic and literal address constructs. This objective is achieved by providing a debugging program which has a complete awareness of the specific machine interfaces, conventions and symbol sets. By essentially stepping through the Assembly language statements (without regard to neighboring statements), the debugging program is able, through such examination, to identify, in the Assembly language program under study, specific instances of the use of statements containing possibly incorrect symbolic or literal address constructs and to run closely related additional tests. The programmer may then examine the denoted Assembly language code to determine if a genuine error exists.

Abstract: A locking device for connectors of printed wired boards, the connectors being of EURODIN (DIN41612C/R) type, which device prevents the disconnection of two coupled connectors, consisting of a rectangular elongated plate in plastic material having four tenons at its corners in relief over said plate, the tenons inserting in end recesses of the connectors when the plate is overlapped to two coupled connectors, the plate further having two resilient end arms, perpendicular to the plate and extending in the same direction as the tenons, each arm having a locking tooth which hooks to the lower side of the connector pair when the plate is overlapped to the coupled connector pair.

Abstract: Instability resulting from the presence of reactive components in the output filter of regulated power supplies of the general type in which regulation is obtained by feeding back the output voltage to the regulator circuitry is eliminated by deriving a feedback signal from the output voltage which includes not only a direct component, but also separately derived first and second derivative components referenced to the reactive characteristics of a series output choke and parallel output capacitor of the output filter circuit. The amplitude ratios of the feedback signal components are selected in accordance with a key aspect of the invention to eliminate the output filter from the characteristic equation of the power supply to thereby eliminate instability whatever its source.

Abstract: Instability resulting from the presence of reactive components in the output filter of regulated power supplies of the general type in which regulation is obtained by feeding back the output voltage to the regulator circuitry is eliminated by deriving a feedback signal from the output voltage which includes not only a direct component, but also separately derived first and second derivative components referenced to the reactive characteristics of a series output choke and parallel output capacitor of the output filter circuit. The amplitude ratios of the feedback signal components and the elements of the local feedback loop of the regulator error amplifier are selected in accordance with key aspects of the invention to eliminate the output filter (including the effective series resistance of the output filter capacitor) from the characteristic equation of the power supply to thereby eliminate instability whatever its source.

Abstract: A protective grounding and referencing arrangement for a high-voltage, high-energy bulk supply is provided in the present invention. Isolation from ground is provided through the use of an isolation transformer connected between the a-c utility supply and the rectifiers which are provided for conversion to d-c. The d-c bus and its energy storage capacitors are then referenced to ground by a high resistance divider network. In such an arrangement the likelihood of an insulation breakdown to ground is significantly reduced. More importantly, in the event that such a breakdown should occur from one or the other terminal of the d-c bus the fault currents that result are limited by the referencing arrangement to a safe level. The energy hazard is thus very significantly reduced for the equipment.

Abstract: In a two-page printer system, there is included a first and second print engine placed on a path in which paper to be printed travels and displaced a distance, L, from one another along the path, the first print engine printing a first side of the paper and the second print engine printing a second side of the paper. The two-page printer system also includes an apparatus for coordinating the printing of the paper, the two-page printer further including a process controller for generating control signals. The apparatus comprises a first storage element for storing information to be printed. A processor element, operatively connected to the first storage element, formats the information to be printed in a form required by the printer, the information to be printed being fetched from first storage element.

Abstract: Memory system and related error detection and correction apparatus wherein the memory, independently on its parallelism, is organized in modules having single byte parallelism, each module having a section with a plurality of bit parallelism for storing SEC-DED codes related to the information stored in the module and wherein a fast memory, addressed with the information codes and the related SEC-DED codes read out from a memory module produces an information output code, corrected as a function of the SEC-DED code, a parity check bit for the corrected information code, and further bits indicative of a corrected single error and a multiple error which cannot be corrected.