Abstract: A mapping between terminal presentation and a Graphical User Interface to an end user using a web browser is provided. The mapping representation is created to support a selected screen image sent from the application to the web browser. A generic interpretative applet and the screen mapping representation is forwarded to a web server and in turn is downloaded to a web browser using a well known protocol. The applet generates and processes messages in an acceptable presentation, e.g. IBM 3270 format, and exchanges those messages directly with a receiving application across a computer network, thereby reducing or eliminating message translation and traffic through intermediate applications and systems.

Abstract: A redundant computer system including two systems capable of independent operation. The two systems correspondingly employ two independent clock generation and distribution (CGD) units which each issue clock and clock definer signals. The clock and definer signals of each system are used internally and are also sent to the other system. When the two systems are split, phase locked loops in each system are disabled, and each system is controlled by a precision oscillator in its own CGD unit When the two systems are merged, one CGD is designated as master and remains under control of its internal oscillator. The clock and definer signals of the master system are employed in the slave system to derive a signal which is used as the reference input to the slave system's phase locked loop from which the slave system's clock and definer signals are developed. Preferably, dual flip-flop phase detector type phase locked loops are employed.

Abstract: Each processor (92) in a data processing system (80) caches a copy of the master calendar clock (97). The master calendar clock (97) and all of the cached calendar clocks (272) are periodically incremented utilizing a common clock (99). Whenever a processor (92) in the system (80) loads the master calendar clock (97) with a new value, that processor (92) broadcasts a cached calendar clock updated interrupt signal (276) to all of the processors in the system. In response to this interrupt (278), each processor (92) clears its cached calendar clock valid flag (274). Whenever a read calendar clock instruction is executed on a processor (92), the flag (274) is tested, and if set, its cached calendar clock (272) value is returned. Otherwise, the master calendar clock (97) value is retrieved, written to that processor's cached calendar clock (272), and returned. The cached calendar clock valid flag (274) is set to indicate a valid cached calendar clock (272).

Abstract: In order to gather, store temporarily and efficiently deliver safestore information in a CPU having data manipulation circuitry including a register bank, first and second serially oriented safestore buffers are employed. At suitable times during the processing of information, a copy of the instantaneous contents of the register bank is transferred into the first safestore buffer. After a brief delay, a copy of the first safestore buffer is transferred into the second safestore buffer. If a call for a domain change (which might include a process change or a fault) is sensed, a safestore frame is sent to cache, and the first safestore buffer is loaded from he second safestore buffer rather than from the register bank.

Abstract: A computer system including a group of CPUs, each having a private cache which communicates with its CPU to receive requests for information blocks and for servicing such requests includes a CPU bus coupled to all the private caches and to a shared cache. Each private cache includes a cache memory and a cache controller including pairs of half-block operand buffers, each divided into quarter block segments. The operand buffer set is coupled to selectively receive, under control of an input multiplexer, requested information blocks from the CPU bus in quarter-block segments and is further coupled to selectively send, under control of an output multiplexer, received quarter-block segments to the CPU and received full blocks to the cache memory.

Abstract: In a coprocessor which processes operands and issues a result word which may include overflow, result and truncation fields and which normally sets a truncation indicator if truncation is employed, the setting of the truncation indicator is inhibited under certain conditions to facilitate later handling of the result. Determinations are made as to whether the result and truncation fields of the result word are zero and as to whether the overflow field is non-zero. If the result and truncation fields are zero, the setting of the truncation indicator is inhibited notwithstanding a non-zero value in the overflow field. Break point position information is processed to obtain masks of bits having logic "1" values for testing the result and truncation fields and logic "0" values for testing the overflow field, the masks then being logically ANDed with the result word. If the result of the ANDing process is a logic "0", the truncation indicator is inhibited from being set.

Abstract: A method allowing the gradual deployment of a new security policy on a data processing system wherein users may access certain objects under the former authorization until complete security implementation is achieved. A user having a security profile satisfying the former security policy criteria, but not the new security criteria, would normally be denied access to objects that were formerly accessible. With the present invention, an intermediate security profile is created while the new policy is being implemented wherein such a user's access is not granted, but not necessarily denied. This tertiary state is achieved by supplementing the security profile of the user to satisfy the new security criteria. When a user attempts object access providing an identity token valid under the former system, arbitration occurs which may result in the synthesis or substitution of a proxy identity which is compliant with the new policy.

Abstract: In order to reduce the size of the memory employed to store firmware, the firmware is written in virtual control words which are then reduced by allotting them to a primary control word memory and at least one secondary control word memory which is addressed by a field in the primary control word memory. A virtual set of secondary control words are each divided into a plurality of fields, and each field of each secondary virtual control word is marked as guarded or "don't care". If a field is marked as "don't care", the function represented by the virtual control word will perform properly no matter what the content of that field. Virtual control word pairs are then examined to ascertain if they can be combined into a single control word.

Abstract: A fault handling process in a computer system subject to CPU design errors and functioning under an operating system (OS) having an integral fault handling module includes the steps of: setting an intercept flag when a central processor fault occurs if the fault is to be directed to a preprocessor; establishing a safestore frame which includes information identifying the type of fault and whether the intercept flag is set; and transferring control to the OS fault handling module; then in the OS fault handling module, determining whether the intercept flag is set; if the intercept flag is not set, handling the fault in the OS fault module; if the intercept flag is set, transferring control from the OS fault module to an Intercept Process written in machine language; and handling the fault in the Intercept Process.

Abstract: A method executed by a computer system for providing a visual interface Nor specifying relationships and correspondences between two graphically displayed database schemas in object oriented form. After displaying two schemas, selecting an object one from each and displaying their attributes. After selecting a pair of attributes if they are key attributes, comparing their domains and recording same and checking to determine if there is a mis-match as to data types. If either attribute is not a key attribute, checking to see if there is a mis- match of data types. If in either case there is no mismatch, then select a name for the combined attribute and deleting the attributes so combined from the list of attributes for each object. Repeating until all attributes of all objects of the two schemas have been combined, then generating a file containing all correspondences and a list of all assertions of correspondences.

Abstract: A computer system including a group of CPUs, each having a private cache which communicates with its CPU to receive requests for information blocks and for servicing such requests includes a CPU bus coupled to all the private caches and to a shared cache.

Abstract: A redundant computer system including two systems capable of independent operation. The two systems correspondingly employ two independent clock generation and distribution (CGD) units which each issue clock and clock definer signals. When the two systems are split, each system is controlled by the oscillator signal generated by its own CGD unit. When the two systems are merged, one oscillator is designated as master, and its output is employed to derive the clock and definer signals on both sides of the redundant system. Special logic included in each CGD unit ensures that the change from master to slave (or slave to master) operation is performed without error. This special logic includes circuitry which places a temporary hold at a predetermined logic level on the local oscillator signal, which is in use when the switch is made, when the local clock and definer signals are both at the predetermined logic level.

Abstract: A method for integrating the schemas of a plurality of independent and heterogeneous database management systems of a distributed database management system (DDBMS). The DDBMS includes a computer system in which the DDBMS resides and one or more subservient computer systems. The schemas of two of the independent database systems are fetched from the subservient computer systems. The schemas are converted from a relational database form to an object-oriented form. The schemas are then normalized and displayed graphically. Equivalencies are identified and the two schemas are integrated. These steps are repeated until the schemas of all data bases to be integrated have been integrated into a single integrated, or global schema.

Abstract: A method executed by a computer system for converting a database schema in relational form to a schema in object-oriented (00) form. The input is the schema of a database in relational form including all relations of the schema and the primary keys, reference keys, and attributes of each relation. A special data structure (SDS) is created for each primary key based on the number of attributes of the key. Each SDS becomes the basis of an object of the 00 schema produced. Attribute functions and cross-reference functions are created based on the SDSs and reference keys. SQL commands to map the relational input schema to the 00 output schema are identified.

Abstract: A method for graphically displaying an object-oriented schema on the screen of a computer system. The input is an object-oriented schema of a database in textual form. The input is parsed to identify the components of the schema. A connectivity matrix is developed in order to determine the number of interrelationships of objects. The screen is partitioned into cells, with each cell designed to hold an object and its attributes, with the object that has the maximum number of relationships with other objects being placed in the center cell of the grid, and related objects in adjacent (surrounding) cells. Relationships between objects and their attributes are identified by lines, arcs, labels, and arrows drawn on the screens of the display device of the computer system. The user can interface with the system by clicking on the graphical objects appearing on the computer screen.

Abstract: A method for improving the efficiency of queries in relational database management systems that use the exhaustive method of query optimization. The join structure of the query is examined prior to query optimization and tables are ordered according to graph theory. The tables in the FROM clause of the query are then reordered before query optimization. The access plan is thus developed from an already near-optimal table ordering. As a result, the number of table permutations examined during query optimization is pruned, the time to examining large numbers of table order permutations is avoided, and the optimization cost is reduced.

Abstract: A redundant computer system including two systems capable of independent operation. The two systems correspondingly employ two independent clock generation and distribution (CGD) units which each issue clock and clock definer signals. When the two systems are split, each system is controlled by the clock and definer signals generated by its own CGD unit. When the two systems are merged, one CGD unit is designated as master, and its clock and definer signals drives both sides of the redundant system. Special logic included in each CGD unit ensures that the change from master to slave (or slave to master) operation is performed without error. This special logic includes circuitry which places a temporary hold at a predetermined logic level on the local clock and definer signals, which are in use when the switch is made, when the local clock and definer signals are both at the predetermined logic level.

Abstract: A data processing system which employs a cache memory feature and a method for lowering the cache miss ratio for called operands in the data processing system are disclosed. Recent cache misses are stored in a first in, first out miss stack, and the stored addresses are searched for displacement patterns thereamong. Any detected pattern is then employed to predict a succeeding cache miss by prefetching from main memory the signal identified by the predictive address. The apparatus for performing this task is preferably hard wired for speed purposes and includes subtraction circuits for evaluating variously displaced addresses in the miss stack and comparator circuits for determining if the outputs from at least two subtraction circuits are the same indicating a pattern yielding information which can be combined with an address in the stack to develop a predictive address.

Abstract: Convoys resulting from competing requests for a popular service are detected and dispersed by a scheduling procedure. When a request first enters the procedure, a determination is made as to whether the procedure is currently in the convoy disperse mode. If not, availability of the service is checked, and if it is available, the request is serviced. If the service is not available, a delay is instituted, and availability of the service is checked again. If it is still not available, a wait-for-service count is checked to determine if it exceeds a predetermined value. If not, the present request is sent to a queued wait. If so, the convoy disperse flag is set true, and the request is sent to the queued wait. If the convoy disperse flag was already true when the request was received into the procedure, a different path is taken in which a loop is entered which involves temporarily relinquishing the processor.

Abstract: In a data processing system which employs a cache memory feature, a method and exemplary special purpose apparatus for practicing the method are disclosed to lower the cache miss ratio for called operands. Recent cache misses are stored in a first in, first out miss stack, and the stored addresses are searched for displacement patterns thereamong. Any detected pattern is then employed to predict a succeeding cache miss by prefetching from main memory the signal identified by the predictive address. The apparatus for performing this task is preferably hard wired for speed purposes and includes subtraction circuits for evaluating variously displaced addresses in the miss stack and comparator circuits for determining if the outputs from at least two subtraction circuits are the same indicating a pattern yielding information which can be combined with an address in the stack to develop a predictive address.