Abstract: Apparatus for monitoring and/or controlling the operations of a computer at a user site from a support center over a telephone line, the computer at the user site including a central processing unit (CPU) and a display terminal. The apparatus includes a telephone instrument at each location connected to the telephone line, a display terminal connected to an acoustic coupler at the support center and a control and switching device at the user site connected to the CPU, to the display terminal at the user site and to an acoustic coupler. When a link is established between the acoustic coupler at the support center and the acoustic coupler at the user site over the telephone line, the display terminal at the support center is operable with the display terminal at the user site in either an on-line mode or a conversational mode. In the on-line mode, either display terminal can input to the CPU and the output from the CPU is displayed at both display terminals.

Abstract: Therein is disclosed high speed digital computer system architecture. System architecture includes a processor for processing machine language digital data and a memory for storing at least machine language instructions for use by the processor. Instructions or data are transmitted between memory and processor by memory input and output busses. Signals are transmitted between computer system and external devices by I/O apparatus. Instruction pre-fetch circuitry is disclosed for fetching from memory, and storing, instructions in advance of instructions being executed by the processor. Also disclosed are a high speed memory and memory input and output busses providing high memory bus bandwidth and simple memory bus interface circuitry. Processor circuitry is disclosed for allowing high speed initiation and execution of instruction sequences. I/O circuitry is disclosed which allows I/O apparatus to easily adapt to a variety of external devices or to changes in computer machine language or instructions.

Abstract: A laser recording system is disclosed in which a beam of light from a laser is split into first and second beams. The first beam is modulated with digital signals from a computer and deflected by a rotating mirror onto the surface of a photoconductive drum. The second beam is deflected by the rotating mirror onto a curved timing plate. The surface of the timing plate is provided with a series of unevenly spaced reflective markings representative of evenly spaced spot positions on the surface of the drum. Light reflected by the timing plate as the second beam scans its surface and strikes the reflective markings impinges on a photodetector located at the center of curvature of the timing plate and is converted by the photodetector into a corresponding series of electrical signals.

Abstract: A data processing system which employs a CPU and a MOS memory, the memory requiring replenishing or refreshing periodically. The CPU includes microcode containing microinstructions, the microinstructions providing control for the CPU including control for the memory. The refreshing scheme employs apparatus for decoding of these microinstructions and for providing refreshing signals to the memory in such a manner that all non-refreshing operations of the data processing system proceed without being delayed by operation of the refreshing apparatus. The algorithm which guides the operation of the CPU includes a number of system operating modes (such as FETCH, MULTIPLY, DIVIDE, HALT, DATA CHANNEL, and others). These modes each contain an operating state designated RAC.fwdarw.MEM which indicates that a refresh signal automatically is forwarded to the MOS memory when a particular operating mode runs through its respective operating states.

Abstract: A microprogrammed processor having a versatile hardware and data path configuration in which control signals for data paths, the ALU function, the shifter and all other control signals are derived from the current microprogram control word which is normally periodically clocked into a ROM buffer. Included are capabilities for effective addressing, incrementing the program counter and computer instruction skips, all while the instruction register is being loaded from memory by direct connection of selected bits of the memory bus to the ROM buffer to derive a micro-instruction. Also included is a conditional skip condition allowing the processor to skip the next instruction by testing selected bits of the instruction register which manipulates the micro-code for this purpose. Another capability is that of hardware structuring to readily accommodate WCS. Other capabilities provide for bit and byte manipulation, allowing the micro-instruction to readily load constants into the ALU, and for marking purposes.

Abstract: An open loop, stepper-motor-driven, rigid magnetic disc memory apparatus for use with a data processing system. A rigid magnetic disc with high track density is driven by a stepper motor in an open-loop fashion or without servomechanism control.

Abstract: A rigid magnetic disc memory apparatus for use with a data processing system. A magnetic read/write head is accurately positioned parallel and adjacent to the plane of a rigid magnetic disc with high track density by a stepper motor in an open-loop fashion without servomechanism control.

Abstract: An open loop, stepper-motor-driven, rigid magnetic disc memory apparatus for use with a data processing system. A rigid magnetic disc with high track density is driven by a stepper motor in an open-loop fashion or without servomechanism control.

Abstract: An open loop, stepper-motor-driven, rigid magnetic disc memory apparatus for use with a data processing system. A rigid magnetic disc with high track density is driven by a stepper motor in an open-loop fashion or without servomechanism control.

Abstract: An open loop, stepper-motor-driven, rigid magnetic disc memory apparatus for use with a data processing system. A rigid magnetic disc with high track density is driven by a stepper motor in an open-loop fashion or without servomechanism control.

Abstract: An open loop, stepper-motor driven, rigid magnetic disc memory apparatus for use with a data processing system. A rigid magnetic disc with high track density is driven by a stepper motor in an open-loop fashion or without servomechanism control.

Abstract: An open loop, stepper-motor-driven, rigid magnetic disc memory apparatus for use with a data processing system. A rigid magnetic disc with high track density is driven by a stepper motor in an open-loop fashion or without servomechanism control.

Abstract: A line power cord voltage-magnitude adaptor is described herein. In a particular embodiment of the present invention, the power plug, line cord, and adaptor plug are pre-assembled as one component of the electrical equipment system; various voltage requirements can thus be prepared-for, whereby the equipment need not be altered, regardless of the eventual market for the equipment. The present invention can be used with virtually all kinds of electrical equipment energized by AC power, including computer systems.

Abstract: There is disclosed a data processing system which employs parallel processors (PP's or P--P's) that are interfaced to the CPU, and which derive their control from microinstructions stored in an extension to the CPU microcode structure. This extension forms part of the CPU/PP interface. The P--P's increase speed of operation of the data processing system in which they are employed by operating synchronously and simultaneously with the CPU when called upon by CPU microcode structure to execute particular algorithms.

Abstract: A single-chip memory-sense amplifier for a data processing system. There is disclosed a sense amplifier (level converter) and bus driver for use in a data processing system, to receive signal inputs from main memory and to drive a memory bus connecting output of the sense amplifier to the CPU. This sense amplifier is intended for use with memory fabricated from N-channel MOS technology. The circuitry of the sense amplifier is fabricated from bi-polar technology and formed on a single monolithic integrated circuit chip. The biasing scheme employed within the circuitry of the sense amplifier provides reliable operation, by making the amplifier relatively insensitive to power supply variations.

Abstract: At least one parallel processor (PP or P-P) is connected between a central processing unit (CPU) interface and main memory for processing certain data simultaneously and synchronously with operation of the CPU. Integrated circuit apparatus for implementing the functions performed by the PP includes an arithmetic and logic unit (ALU), a set of registers, microprogrammable circuitry (RAM's, ROM's, PROM's) and other integrated circuitry. The PP includes decode and control apparatus, which decodes microinstructions stored in an extension to the control store of the CPU, the extension forming part of the CPU/P-P interface, and thereafter employs the decoded microinstructions to control operation of the P-P.

Abstract: A method of reading on a record medium a two level code representing at least one character of a set of characters, each character having six consecutive transitional occurrences between the two levels of the code comprising: scanning the record medium to derive a time based electrical signal representative of said transitional occurrences; measuring four periods between alternate ones of said transitional occurrences; comparing each two overlapping periods to generate three ratios, each ratio representing not more than one of three possible values of nearly one, smaller than one and larger than one, and; decoding the values arrived at for said three ratios to define a character. The arrangement of the coded indicia on the record medium or the font of type for imprinting the same is such that, for each character, not more than two bits of the same level are arranged consecutively and two consecutive bits of a first level are not immediately followed by two consecutive bits of a second level.

Abstract: An improved plasma etching process. There is disclosed apparatus and method (or process) for etching patterns in metal films deposited on a semiconductor wafer. This improved process is particularly useful in the fabrication of certain semiconductor devices, such as MOS and bipolar integrated circuits and Schottky transistors (semiconductor/metal interfaces) which employ contact "fingers". The fingers are constructed from layers of metal, such as aluminum, tungsten, and titanium with aluminum being the outermost layer.

Abstract: An improved method of fabricating metal-semiconductor interfaces such as Schottky barriers and ohmic contacts. There is disclosed apparatus and method (or process) for chemically converting, etching, or passivating the surface of a material, such as the surface of a silicon wafer, in a gaseous plasma environment consisting of atomic, neutral nitrogen which causes the surface of the material to be resistant to otherwise subsequent nascent surface oxide buildup. This process is particularly useful in manufacture of Schottky diodes, transistors, and other electronic components or discrete and integrated devices requiring high quality metal-semiconductor junctions or interfaces.