Abstract: There is disclosed an input/output system, employed within a data processing system that includes a central processing unit (CPU). The CPU includes improved input/output shift register structure of interfacing structure for interfacing with I/O structure. The I/O structure includes improved CPU transceiver and peripheral device transceiver apparatus. The device transceiver interfaces with an improved device controller. In the preferred embodiment of the present invention, the CPU, CPU transceiver, device transceiver, and device controller, all being constructed primarily from MOS technology, are each contained within a respective chip. Further features of the input/output system include capability for placement of multiple transceiver/controllers and their respective peripheral devices at varying distances from the CPU by virtue of novel clock and data transmission means which maintains accurate processing of data regardless of propagation delay, distortion, data skewing, etc.

Abstract: There is disclosed an input/output system, employed within a data processing system that includes a central processing unit (CPU). The CPU includes improved input/output shift register structure or apparatus for interfacing with an I/O bus (bus structure). The I/O structure includes improved CPU transceiver and peripheral device transceiver apparatus. The device transceiver interfaces with an improved device controller. In the preferred embodiment of the present invention, the CPU, CPU transceiver, device transceiver, and device controller, all being constructed primarily from MOS technology, are each contained within a respective chip. Further features of the input/output system include capability for placement of multiple transceiver/controllers and their respective peripheral devices at varying distances from the CPU by virtue of novel clock and data transmission means which maintains accurate processing of data regardless of propagation delay, distortion, data skewing, etc.

Abstract: A microprogrammed processor in which control signals for data paths, the ALU function, the shifter and all other control signals are derived from the current microprogram control word which is normally periodically clocked into a ROM buffer. The processor provides for microbranching capability with and/or without a test, testing capabilities including direct addressing with simultaneous temporary address storage capability for future recall, and selective testing of computer instruction bits for decoding to address the next micro-instruction. Additional capabilities provide for flexible access to the micro-code instruction control store through a ROM address multiplexer which allows for selection of at least one of four possible micro-instruction addresses determined by micro-code control decode logic.

Abstract: There is disclosed an input/output system, employed within a data processing system that includes a central processing unit (CPU). The CPU includes improved input/output shift register structure or interfacing means for interfacing with I/O means (bus structure). The I/O means includes improved CPU transceiver and peripheral device transceiver apparatus. The device transceiver interfaces with an improved device controller. In the preferred embodiment of the present invention, the CPU, CPU transceiver, device transceiver, and device controller, all being constructed primarily from MOS technology, are each contained within a respective chip. Further features of the input/output system include capability for placement of multiple transceiver/controllers and their respective peripheral devices at varying distances from the CPU by virtue of novel clock and data transmission means which maintains accurate processing of data regardless of propagation delay, distortion, data skewing, etc.

Abstract: There is disclosed an MOS pulse-edge detector circuit. In certain applications it is desirable or necessary for an MOS switching circuit to respond substantially simultaneously to an edge of a control pulse. The present invention relates to a novel MOS component design which utilizes inherent or intrinsic capacitance thereof in a manner to detect and respond to an edge of a pulse such as a control or clock pulse at the time of occurrence of that edge.

Abstract: The present invention relates to an improved MOS memory structure. There is disclosed an array of memory cells of the three-device-per-bit type, the array being formed in rows and columns. Temporary storage cells are disclosed which are employed to receive and temporarily store inverted digital information from selected memory cells responsive to a READ signal. The inverted digital information is re-inverted upon restoration thereof into the selected memory cells, thus eliminating any need of accounting for the polarity or status of the data, whereby propagation delay time through the memory structure is reduced.

Abstract: A microprogrammed processor having a versatile hardware and data path configuration in which control signals for data paths, the ALU function, the shifter and all other control signals are derived from the current microprogram control word which is normally periodically clocked into a ROM buffer. Included are capabilities for effective addressing, incrementing the program counter and computer instruction skips, all while the instruction register is being loaded from memory by direct connection of selected bits of the memory bus to the ROM buffer to derive a micro-instruction. Also included is a conditional skip condition allowing the processor to skip the next instruction by testing selected bits of the instruction register which manipulates the micro-code for this purpose. Another capability is that of hardware structuring to readily accommodate WCS. Other capabilities provide for bit and byte manipulation, allowing the micro-instruction to readily load constants into the ALU, and for marking purposes.

Abstract: A method of reading on a record medium a two level code representing at least one character of a set of characters, each character having six consecutive transitional occurrences between the two levels of the code comprising: scanning the record medium to derive a time based electrical signal representative of said transitional occurrences; measuring four periods between alternate ones of said transitional occurrences; comparing each two overlapping periods to generate three ratios, each ratio representing not more than one of three possible values of nearly one, smaller than one and larger than one, and; decoding the values arrived at for said three ratios to define a character. The arrangement of the coded indicia on the record medium or the font of type for imprinting the same is such that, for each character, not more than two bits of the same level are arranged consecutively and two consecutive bits of a first level are not immediately followed by two consecutive bits of a second level.

Abstract: A hand-operated scanner having an inverted T-shaped extension for slideably receiving two adjacent fingers for manipulating the scanner and simultaneously allowing the operator's fingers to remain free for merchandise packaging, merchandise check-out and/or making keyboard entries by artful placement of the extension in relation to the scanner reading head.

Abstract: A water recycle treatment system comprising two main treatment sub-systems for treatment of contaminated water from a plurality of concentrated solutions and rinse baths to separate out the impurities therein. A first sub-system treats less concentrated solutions used for the rinse baths by channeling the flow therefrom to a first neutralizing tank which provides for pH control to produce a mixed output solution having a substantially constant pH factor, which is filtered to remove gross particles, the filtered solution being cooled in a holding tank and passed through a reverse osmosis process and carbon bed to produce clean water. The second sub-system treats highly concentrated solutions obtained from a plurality of chemical processes, mixes them in a second neutralizing tank which is utilized to produce a substantially constant pH output, which is fed to an evaporator to precipitate the metals and salts in sludge and also forms a water vapor output.

Abstract: A digital magnetic tape transport incorporates a pair of adjacent vacuum storage columns each with oppositely disposed closed and open ends, a magnetic head assembly defining a generally linear tape threading path along one side of the vacuum storage columns and substantially parallel to the vacuum columns lengthwise direction, a pair of tape storage reels mounted at a second side of the vacuum storage columns positioned along a line substantially parallel with the linear tape threading path, whereby a rear closed end of the vacuum column adjacent to a storage reel is tapered at an angle substantially tangent to the adjacent storage reel, allowing for: elimination of an idler roller; an improved take-up path, and; for easier manual threading of the tape. A similar tapered configuration is provided at the rear end of the second vacuum column also eliminating the necessity of an idler roller.

Abstract: In a digital computer system having a main memory operable at a first speed, a high speed buffer operating at a second speed for temporarily storing selected portions of the main memory, an associative memory for temporarily storing selected main memory addresses and comparing the stored addresses with a newly received address in a read/write operation to generate comparison data, a read only memory a bit configuration reflecting an algorithm, connected to the associative memory for generating a new order of priority for the memory address stored in the associative memory, and a storage unit connected from the read only memory for storing that order of priority for subsequent feedback to the read only memory in a subsequent cycle as a previous order of priority.

Abstract: A system for automatically maintaining a record for an order of data priority of data stored in locations of an associative memory which compares the data stored in the locations with newly received data to generate a comparison output and where the order of priority is based on usage of data, comprising a read only memory a bit configuration reflecting an algorithm, connected from the associative memory for generating a first set of signals defining the least recently used location of the associative memory and for generating a second set of signals defining the order of word priority in terms of the associative memory locations, and a storage unit for receiving the second set of signals for subsequent feedback to the read only memory for re-defining the word priority as effected by newly received data.

Abstract: A tape loading system for use with tape transport systems having low inertia tape loops formed in vacuum buffer columns in a tape path between the tape storage reels and the tape driving means comprising, a vacuum source for providing vacuum in the vacuum buffer columns and ascertaining a predetermined value of build-up of vacuum in the columns and upon attaining the predetermined vacuum value supplying a predetermined length of tape from the tape storage reels to each of the buffer columns. A tape unloading arrangement also provides for automatically ensuring rewind, then shutting off the vacuum source, and then applying sufficient bias for slight rotation of the storage reels to unwind the tape.