Abstract: A container assembly for carrying display-packaged delicate baked goods includes a container having opposing side walls interconnected with opposing end walls, a bottom interconnected with each of the side and end walls, a top, and an interior. A retaining tray has at least one aperture therein, and is removably received in the container interior. The retaining tray is dimensioned such that the container side and end walls restrict movement of the retaining tray in a direction perpendicular to the container side and end walls. The retaining tray includes at least one spacing member extending therefrom and spacing the retaining tray from an underlying surface. A display package includes a pan portion and a top removably secured to the pan portion. The pan portion includes a projection extending outwardly therefrom, and is removably received within the aperture until the projection contacts the retaining tray.

Abstract: The resistance to current flow through an MOS-gated semiconductor device is reduced by providing a high conductivity region in the path of current through the drain region, but so positioned relative to the p-n voltage blocking junction of the device so as not to adversely affect the voltage blocking capability of the p-n junction. In one embodiment, the drain region is made of higher than normal electrical conductivity, but a diffused, graded p-n junction is provided for extending the low conductivity portion of the drain region bordering the p-n junction further than usual into the drain region.

Abstract: An alloy for galvanizing steel comprises, by weight, aluminum in the amount of at least 0.001% to 0.007%, preferably 0.002 to 0.004%, tin in the amount of at least 0.5% to a maximum of 2%, preferably at least 0.8%, and one of an element selected from the group consisting of vanadium in the amount of at least 0.02%, preferably 0.05% to 0.12%, titanium in the amount of at least 0.03%, preferably 0.06% to 0.10%, and both vanadium and titanium together in the amount of at least 0.02% vanadium and at least 0.01% titanium for a total of at least 0.03%, preferably 0.05% to 0.15%, the balance zinc containing up to 1.3 wt. % lead. In another embodiment, the alloy comprises, by weight, aluminum in the amount of at least 0.001%, tin in the amount of 0.5% to 2%, and vanadium and nickel together in the amount of at least 0.02% vanadium and at least 0.02% nickel to a maximum of 0.15% vanadium and nickel collectively. Titanium may be added in an amount, by weight, of at least 0.01% titanium to a collective maximum of 0.

Abstract: In one embodiment a substrate 14 is patterned to have high and low conductive areas 110, 112, respectively. Metal lines 104, 108 in dielectric layer 16 pass transversely over the areas 110, 112. The areas 112 interrupt parasitic inductive current induced in the substrate 14.

Abstract: A multi-phase DC/DC converter having an output voltage and including a plurality of converter channels. Each converter channel includes a converter channel input and a converter channel output. Each converter channel is configured for generating a converter channel current and for adjusting said converter channel current in response to a control signal electrically connected to each converter channel input. A control circuit generates an error signal representative of a comparison of the converter output voltage to a reference voltage. The control circuit includes a plurality of control circuit channels, each of which correspond to a converter channel. Each control circuit channel generates a channel current signal representative of a corresponding converter channel current, and generates a differential channel current signal representative of a comparison of the channel current signal to an average current signal.

Abstract: The present invention induces provides a gettering trench on the front surface of a device substrate. In one embodiment it induces stress and simultaneously forms a gettering zone 40 for gettering impurities in an integrated circuit structure. In another embodiment, the trench is filled with gettering material 72 such as polysilicon. The two gettering mechanisms may be combined 82,84. The invention is useful for providing gettering in bonded wafers and in silicon-on-insulator devices (FIGS. 4,5).

Abstract: An IGBT gate driver circuit includes means for detecting when the collector-to-emitter voltage (Vce) of a turned-on IGBT, intended to be operated in the saturation region, increases above a preset level, indicative of a fault condition, such as a short circuit. In response to such an increase in the Vce of a turned on IGBT, the IGBT is turned-off in two steps. First, the turn-on gate drive is decreased to a level that is still above the threshold (turn-on) voltage of the IGBT in order to decrease the current flowing through the IGBT and hence, the peak power dissipation. This decrease in the current through the IGBT and the peak power dissipation increases the length of time the IGBT can withstand a fault condition such as a short circuit. Then, after decreasing the gate drive to the IGBT, the gate drive is gradually decreased until the IGBT is completely turned off.

Abstract: A reservoir pump assembly for use with a container having a fill opening and an interior includes an annular, elongate reservoir casing configured for being inserted into the fill opening of the container and for being disposed substantially entirely within the interior of the container. The reservoir casing defines a pressure chamber configured for containing fluid under pressure. An annular, elongate guide cylinder is disposed substantially entirely within the pressure chamber and defines an inlet orifice and an outlet orifice. The outlet orifice interconnects the guide cylinder and the pressure chamber. The inlet orifice interconnects the guide cylinder and the interior of the container. An inlet valve is associated with the inlet orifice, and an outlet valve is associated with the outlet orifice. An elongate pump rod is disposed partially within the guide cylinder and is configured for reciprocating movement therein. The pump rod has a first end and a second end.

Abstract: A unique fashion or sports hat or cap assemblage having a brim or bill/visor, distinctly designed with a sliding mechanism to rotate the brim or bill/visor up to 360 degrees without detachment from the crown of the cap or hat, including interchangeable and multiple options for the crown, body and visor portions and in which the sliding mechanism is attached to a headband and the headband in turn attached to an intermediate elastic material also attached to the periphery of the crown.

Abstract: In an improved cover and drainage device for a swimming pool, the cover has an upper surface sealably connected to a drain that enables accumulated water on the surface to drain into a sealably connected drainage conduit disposed within the pool. The conduit extends through a pipe attached to an external surface of a side wall of the pool and terminates in a water discharge outlet external to the pool. The improvement comprises flexible means for sealably securing the drainage conduit to the pipe, thereby enabling movement of the conduit relative to the pipe.

Abstract: A precision resistor of NiCr or SiCr has a refractive and thermal barrier layer beneath the resistor. The refractive barrier is a layer of refractory metal. The refractory metal prevents the incident laser beam of a laser trimmer penetrating lower layers of the device. Unwanted reflections and refractions caused by lower layers are avoided. The reflective barrier layer is a material selected from the group consisting of tungsten, titanium, molybdenum, TiSi2l3,14, CoSi215, MoSi2, TaSi2 and WSi2.

Abstract: In a method for forming a bonded semiconductor-on-insulator substrate for the fabrication of semiconductor devices and integrated circuits, a surface of a wafer of a monocrystalline semiconductor material is implanted with ions of the semiconductor material a to a selected depth in the wafer to form, adjacent to the surface, an amorphous layer of the semiconductor material. The layer of amorphous semiconductor material extends to a substantially planar zone disposed at substantially the selected depth and comprising the monocrystalline semiconductor material damaged by lattice defects, i.e., end-of-range implant damage. Undamaged material below the selected depth comprises a first layer of the monocrystalline semiconductor material.

Abstract: A high Q low pass filter removes the carrier from a Class D amplifier. Speaker impedance varies with frequency, and it is desirable for to drive 2, 4 and 8 ohm speakers. The bandwidth feedback compensation network 800 adds a pole-zero combination to the feedback loop to reduce the Q of the low pass filter and to maintain the bandwidth of the amplifier.

Abstract: A power trench MOS-gated transistor is constructed with a buried gate to source dielectric inside a gate trench region. In the innovative device, a thick oxide (grown or deposited) is used to define the height of the trench walls. A body region is initially formed by selective epitaxial growth and etch back. Source regions are formed also by selective epitaxial growth. The body is finally formed by selective epitaxial growth and etch back. The oxide is removed from the trench, the trench walls are oxidized to form a gate oxide, and doped polysilicon fills the trench to form a gate. By the formation of the source region using the spacer etch, this process simplifies the fabrication of power trench gated devices, and provides for increased contact surface area without increasing device size.

Abstract: A DC to DC buck pulse width modulator converter circuit includes an input, a high side output and a low side output. A high side switch is electrically connected between a common output node and a voltage supply, and controls a flow of current therethrough dependent upon the high side output. A low side switch is electrically connected between the common output node and ground, and controls a flow of current therethrough dependent upon the low side output. A virtual ground amplifier includes a second input electrically connected to ground. A current feedback resistor is electrically connected intermediate the common output node and a first input of the virtual ground amplifier. A variable impedance component is electrically connected to an output of the virtual ground amplifier and to the first input of the virtual ground amplifier. The impedance of the variable impedance component is varied dependent upon the output of the virtual ground amplifier.

Abstract: A silicon semiconductor die comprises a heavily doped silicon substrate and an upper layer comprising doped silicon of a first conduction type disposed on the substrate. The upper layer comprises a well region of a second, opposite conduction type adjacent an edge termination zone that comprises a layer of a material having a higher critical electric field than silicon. Both the well region and adjacent edge termination zone are disposed at an upper surface of the upper layer, and an oxide layer overlies the upper layer and the edge termination zone. A process for forming a silicon die having improved edge termination. The process comprises forming an upper layer comprising doped silicon of a first conduction type on a heavily doped silicon substrate, and forming an edge termination zone that comprises a layer of a material having a higher critical electric field than silicon at an upper surface of the upper layer.

Abstract: A device for influencing the handling characteristics of remote-controlled model cars or model ships, comprising a first input terminal for a first control signal which represents a first command variable which can be specified by a person who controls the vehicle, a sensor means which outputs a second control signal which represents a disturbance variable correlated with the rotational velocity or the lateral acceleration of the model vehicle, and a processing means which is connected with the first input terminal for receiving the first control signal and which has a second input terminal for receiving the second control signal, and which generates a first output signal which represents a first manipulated variable being a function of the first command variable and of the disturbance variable, with the first manipulated variable generated by the processing means being the command variable which as a function of the disturbance variable is limited or modified to a predeterminable degree.

Abstract: In a process for forming an MOS-gated device having self-aligned trenches, a screen oxide layer and then a nitride layer are formed on an upper layer of a semiconductor substrate. The nitride layer is patterned and etched to define a well region in the upper layer, and ions of a first conductivity type are diffused into the masked upper layer to form the well region. Ions of a second, opposite conductivity type are implanted into the well region to form a source region extending to a selected depth that defines a source-well junction. After removal of the well mask to expose the previously masked portion of the nitride layer, an oxide insulating layer providing a hard mask is formed overlying the well and source regions. The remaining previously masked portions of the nitride layer and underlying screen oxide layer are removed to expose the portion of the substrate not masked by the oxide insulating layer.

Abstract: A method for fabricating a field effect transistor using the supporting substrate as a device layer in accordance with the present invention comprises several steps. To fabricate the field effect transistor, an epitaxial layer is grown on one surface of a substrate having an opposing surface, the epitaxial layer forming a drain for the transistor. Once the epitaxial layer is grown, the substrate is thinned to an appropriate device thickness and then a gate and a source for the transistor are formed on the opposing surface of the substrate. In an alternative embodiment, a polysilicon layer is used instead of the epitaxial layer. A field effect transistor fabricated from the method described above includes an epitaxial layer formed on one surface of a substrate having an opposing surface, the epitaxial layer forming a drain for the transistor and a gate and a source for the transistor formed on the other surface of the substrate.