Abstract: A multimode comb filter for comb filtering, e.g., NTSC and/or PAL video signals includes delay means for concurrently providing video signals representing first, second and third adjacent horizontal lines. First and second combining means coupled to the delay means provide alternate 1-H comb filtered signals in both the NTSC and PAL modes. Control circuitry coupled to the delay means generates a control signal for adaptively selecting the one of the alternate 1-H comb filtered signals or appropriate proportions of both alternate 1-H comb filtered signals to form an output comb filtered signal. In the NTSC mode the control circuitry generates the control signal from sums of vertically aligned pairs of samples from said first and second lines and from said second and third lines. In the PAL mode the control signal is generated from alternating sums and differences of vertically aligned pairs of samples from said first and second lines and from said second and third lines.

Abstract: A video signal transmission system includes adaptive compansion circuitry to improve the signal-to-noise ratio of transmitted signals. A compandor at the transmitter, and corresponding inverse compandor at the receiver, are arranged to have a plurality of selectable compansion transfer characteristics. Selection of particular ones of the transfer characteristics is responsive to, e.g., predicted values of current signal.

Abstract: A multimode comb filter for comb filtering, e.g., NTSC and/or PAL video signals includes delay means for concurrently providing video signals representing three adjacent horizontal lines. First and second combining means coupled to the delay means provide alternate 1-H comb filter signals in both the NTSC and PAL modes. Control circuitry coupled to the delay means generates a control signal for adaptively selecting the one of the alternate 1-H comb filtered signals or appropriate proportions of both alternate 1-H comb filtered signals to form an output comb filtered signal.

Abstract: A digital signal clamp circuit is realized using an adder and an up/down counter. The digital signal is coupled to one input of the adder and the counter output is coupled to a second input of the adder. The up/down counter is enabled to count only during signal intervals exhibiting the desired clamping level. The counter is controlled to count up or down depending on the polarity of the signal provided by the adder. The count value in the counter is continuously applied to the adder to provide clamping. Using a truncated count value from the counter enhances clamping performance.

Abstract: A picture-in-a-picture television receiver displays a compound image which includes a compressed image derived from an auxiliary signal inset in a full-size image derived from a main signal. The auxiliary composite video signal is sampled synchronous with a system clock signal that is burst locked to the main signal. The sampled data signal is separated into luminance and color information component signals, which are subsampled and stored in a field memory synchronous with the system clock signal. The clock signal phase used for horizontal subsampling is determined at the start of each line to compensate for skew errors in the auxiliary signal. The luminance samples retrieved from the memory are applied to clock transfer circuitry which resynchronizes the samples to a phase shifted version of the system clock signal to compensate for skew errors in the main signal. The phase shifted clock signal is synchronized to the horizontal scanning signals used to display the compound image.

Abstract: A video processing system includes apparatus for panning and magnifying portions of a source image stored in memory. Viewer control circuitry generates center coordinates of the portion of the image to be displayed and also a magnification factor. Further circuitry, responsive to the center coordinates and the magnification factor, generates starting addresses for reading the appropriate portion of the source image from memory. The system monitors the relative values of the center coordinates and the magnification factor to preclude blanking intervals of the source image from being displayed.

Abstract: A comparator circuit for operation at video rate signals includes input switches to alternately couple a reference and a signal potential to a summing capacitor. The capacitor is coupled to the input of a first inverting amplifier. The amplifier includes a switch between input and output terminals for selectively autozeroing the amplifier. The amplifier is direct coupled to the input of a second inverting amplifier having an autozero circuit exclusive of a connection to the input of the second amplifier. Timing circuitry for controlling the autozero function is arranged to minimize the effects of clocking transients upsetting the autozeroed potentials thereby reducing the response time and enhancing the sensitivity of the comparator.

Abstract: A picture-in-a-picture television receiver includes a memory for holding samples representing a vertically and horizontally compressed image. The memory is divided into three parts, a main portion which holds one field of the compressed image and first and second crossover buffers, each of which hold one line of the compressed signal. Both upper and lower field types may be derived from each field of the auxiliary signal used to produce the compressed image. Sample values are stored into the memory such that an upper field of the compressed image is stored when an upper field of the main image is displayed and a lower field is stored when a lower field is displayed. When the address used to read samples from the memory overtakes the address used to write samples into the memory, the type of field derived from the auxiliary signal is switched and one line of samples is directed to one of the crossover buffers.

Abstract: A word serial multiplier includes a first circuit loop for loading a parallel-bit multiplier, and in response to a clock signal sequentially produces a gate signal corresponding to a sequence of bits of the multiplier sample in descending order of significance. A second circuit loop loads a multiplicand sample and in response to the clock signal successively divides the multiplicand sample by the factor two. The more significant bits, exclusive of the least significant bit, of the divided multiplicand sample are coupled to a gating circuit. The gating circuit passes the more significant bits to the input of an accumulator if the corresponding bits of the gate signal exhibit a predetermined state. After a number of cycles of the clock signal, corresponding to the number of bits m of the multiplier sample, the accumulator produces a scaled product equal to the muliplicand times the multiplier times the scale factor of 2.sup.-(m-1).

Abstract: A digital D.C. control system includes a multiplexer, a digital-to-analog converter, a capacitor, offset generating circuitry and clamping circuitry. A digital signal to be D.C. controlled and a digital brightness control signal are alternatively coupled by the multiplexer to the input of the digital-to-analog converter. The output from the digital-to-analog converter is coupled to a system output terminal via the capacitor. When the signal is applied to the digital-to-analog converter a fixed D.C. offset is applied to the interconnection of the converter and capacitor. During preselected intervals the D.C. control value is coupled to the digital-to-analog converter concurrently with the system output terminal being clamped to a fixed reference and the D.C. offset circuitry being disabled. This combination of apparatus permits controlling the D.C. level of a digitally processed signal without affecting the dynamic range of the digital signal.

Abstract: A matrix display apparatus fabricated in low mobility material includes integrated commutating circuitry for applying data signals to the display elements. The commutating circuitry includes demultiplexing circuitry coupled to a first set of latch elements. These latch elements are coupled to a second set of latch elements via transmission gates, and the output terminals of the second set of latch elements are coupled to column buffers. The demultiplexing circuitry includes pass transistors to coupled display signals to respective ones of the first set of latches. The first set of latches are preconditioned by appropriate timing signals so that the demultiplexor pass transistors operate in a common source mode to shorten the overall switching time of the commutating circuitry.

Abstract: Comb filter apparatus for comb filtering NTSC or PAL video signals includes sampling circuitry to sample the video signal at 45 degrees relative to the I,Q or U,V axes. The sampled signal is coupled to delay circuitry arranged to concurrently provide video samples from three successive horizontal lines, designated top, middle and bottom. The video samples from the middle line are combined with samples alternately selected from the top and bottom lines to provide a comb filtered signal.

Abstract: Apparatus for augmenting a television signal with auxiliary signal includes circuitry for modulating a picture carrier with baseband video signal to generate a vestigial sideband television signal. Auxiliary signal is modulated on a further carrier of such frequency that the upper sidebands of the modulated further carrier, representing the auxiliary information, (1) occupy the frequency spectrum of the vestigial sideband of the vestigial sideband television signal and (2) occur clustered at odd multiples of half line frequency. The sidebands of the modulated further carrier are added to the vestigial sideband television signal in frequency interleaved fashion in the vestigial sideband spectral region.

Abstract: Area enlargement of television pictures can be achieved by stretching the picture at the same time in the vertical and horizontal directions. In the simplest case this can be accomplished by increasing the scanning amplitude. As the horizontal deflection consumes the greatest part of the energy converted in a picture reproduction apparatus and as it requires high-powered modular elements, an increased scanning amplitude would undesirably augment the energy consumption and further increase the demand on the performance of the modular elements in use. Image enlargement according to this invention is accomplished by storing the horizontally succeeding picture information of a just transmitted or reproduced scanning line and by subsequently displaying the sequential picture information of an area of the scanning line stretched over the whole horizontal period.

Abstract: A video signal processor as for generating a picture-in-picture signal, generates respective analog luminance components and first and second analog chrominance components. In order to reduce the system hardware and processing speed, multiplexing circuitry subsamples the luminance and chrominance components on a field basis to provide alternating fields of only luminance and only chrominance signal. The multiplexing circuitry further subsamples the chrominance components by providing groups of horizontal lines of only the first chrominance component alternating with groups of horizontal lines of only the second chrominance component.

Abstract: A television system for generating video signals for reception by a receiver having adaptive processing circuitry susceptible of errors includes circuitry for emulating portions of the receiver and detecting the occurrences of such errors. A signal representing the occurrences of the errors is generated and combined with the transmitted video signal. At the receiver the error signal is separated from the video signal and utilized by the adaptive processing circuitry to ameliorate the effects of such errors.

Abstract: A method and apparatus for determining the value of a sample having a particular position in an ordered ranking, by magnitude, of a set of digital samples includes means for truncating the lesser significant bits of the samples. Further means compares the values of the truncated samples and generates selection control signals indicating the truncated sample which is in the desired position of an ordered ranking of the truncated samples. A function generator then generates a function of the samples, corresponding to the selected truncated samples.

Abstract: An amplifier/limiter circuit includes an amplifier providing an output signal having a potential range between ground and V.sub.D volts. A first pair of parallel connected complementary transistors have their principal conduction paths coupled between the output terminal of the amplifier and an amplifier/limiter output terminal. A second pair of parallel connected complementary transistors have their principal conduction paths coupled between the amplifier/limiter output terminal and a point of reference potential having a potential value between V.sub.D and ground. The amplifier/limiter output terminal provides a linear, amplified version of signal provided to the amplifier circuit over a limited range of potentials between V.sub.D and ground, which range is less than V.sub.D.

Abstract: Apparatus and method of synchronizing the component signals of a multi-component augmented television signal between its generation reception are disclosed. The disclosed apparatus includes circuitry which generates a training signal that indicates the position of the first pixel in each horizontal line interval of the video signal. This training signal is inserted into one horizontal line interval of the active video signal for transmission. The receiver includes circuitry which separates the training signal and derives a timing signal from it. The timing signal is used to define the pixel positions of various decoded components of the received video signal to facilitate their combination. The timing signal is also used to align the color subcarrier signal and to generate other carrier and subcarrier signals used in the decoding process. Two training signals are disclosed: a pseudo-random noise sequence and a time-reversed, all-pass filtered, raised-cosine 2T pulse.

Abstract: A sampled data FM demodulator samples the FM signal at intervals of (2n.pi.+.pi./2) radians relative to the FM carrier. Pairs of samples S.sub.n and S.sub.n+1 are square and multiplied together to generate sample values S.sub.n.sup.2, S.sub.n+1.sup.2 and S.sub.n S.sub.n+1. These sample values are lowpass filtered in a filter having a cutoff frequency which substantially attentuates at least the second harmonic of the FM carrier. The low pass filtered samples are then combined according to the relation S.sub.n S.sub.n+1 /.sqroot.S.sub.n.sup.2 S.sub.n+1.sup.2 to generate demodulated output samples.