Abstract: Circuitry for recognizing an authorization code included in a video signal for enabling a subscriber's television receiver, includes quantizing apparatus for coarsely quantizing the received signal. A correlator designed to recognize the authorization code is coupled the quantizer and produces an array of correlation values. The correlation values are coupled to a threshold circuit which converts the correlation values to bistate values. Further circuitry evaluates the distribution of bistate values to determine reception of the authorization code.

Abstract: A digital-to-analog converter includes a sampled data sigma-delta modulator to resample and coarsely quantize the digital samples to be converted. The coarsely quantized samples are converted to sequences of pulses which are applied to a pulse sensitive analog integrator to develop analog representations of the digital signal.

Abstract: A programmable sampled data subsampling system includes a programmable antialias filter which bandlimits the information bandwidth of the signal to be subsampled in accordance with the subsampling rate. The antialias filter includes a recursive filter which scales and combines input samples and delayed combined samples in proportions of K and (1-K) where K is a variable. The variables K are applied to the recursive filter in repeating sequences of N values of K where N is the subsampling factor. Every N.sup.th combined sample is extracted and provided as the subsampled signal.

Abstract: In an audio signal amplitude control circuit of the type including a tapped resistive divider to which the signal is applied, and a multiplexer for selecting one of a plurality of differently attenuated signals from said taps responsive to control signals, the selected signal will include switching transients due to capacitive coupling with the control signals. The switching transients are substantially eliminated by including a second tapped resistive divider to which antiphase input signal is applied, and a second multiplexer coupled to the taps of the second divider. Output signals from the multiplexer and second multiplexer are coupled to a differential amplifier which cancels the switching transients generated by the two multiplexers and constructively combines the useful signal components from the two multiplexers.

Abstract: A phase locking system for providing a sampling signal which is to be phase/frequency locked to an applied signal includes a controllable oscillator coupled to a sampling circuit to produce samples of the applied signal representing substantially quadrature phase related components of the applied signal. An accumulator respectively accumulates the quadrature phase components over predetermined intervals. A differencing circuit successively forms the differences of one of the components from successive intervals. The differences are used to generate a control signal to alter the signal generated by the controllable oscillator.

Abstract: Extended definition television (EDTV) signals including a compatible composite wideband signal and a separate helper or extended definition signal are combined, for example, for recording purposes, using frequency multiplexing techniques. The helper signal is applied to a modulator, which produces a suppressed carrier modulated signal, to frequency shift the helper signal to a spectral band above the frequency band occupied by the compatible composite wideband signal. The frequency shifted and wideband signal are then added to form the combined signal.

Abstract: Integrated latch circuitry for driving row or column busses of a matrix device fabricated in low mobility semiconductor material includes cross coupled transistors having variable impedance load devices. The cross coupled transistors are coupled between relatively positive and relatively negative supply potentials. The relatively negative supply potential is modulated to preset the state of the latches in order to reduce the load on input circuitry applying data to the latch. The variable impedance loads are modulated between relatively high and relatively low impedances to enhance the speed at which the latches change state.

Abstract: An asymmetrical sideband modulated (ASM) signal, such as an RF NTSC television signal is demodulated into in-phase and quadrature phase components, each of which are sampled at a sampling rate that is less than the Nyquist rate for the components. The signals, each of which includes aliasing distortion, are respective real and imaginary parts of a complex signal that is not subject to aliasing distortion at the chosen sampling frequency. The in-phase component of the signal is recovered by inserting zero-valued samples interstitially into each of the sampled in-phase and quadrature phase signals and then applying the modified signals to a complex filter. The resultant interpolated in-phase signal is a full bandwidth signal and is substantially free of aliasing distortion.

Abstract: A control signal spreader for ameliorating undesirable effects of abrupt changes in a control signal in a video signal processor gradually changes the magnitude of the control signal in the horizontal, vertical and temporal dimensions of the video signal. The control signal is applied to a first circuit, which, responsive to positive transitions of the control signal, generates a gradually increasing signal and provides the lesser valued one of the control signal and the generated signal. A delayed version of the control signal is applied to a second circuit, which, responsive to negative transitions of the control signal, generates a gradually decaying signal and provides the greater valued one of the control signal and the generated decaying signal. The first and second circuits are coupled to a third circuit which provides as an output control signal, the greater valued signal provided by the first and second circuits.

Abstract: A digital TV receiver includes an apparatus for generating a skew corrected clock. The apparatus consists of a fixed frequency, free running oscillator for producing a signal having a frequency which is a fixed integer multiple K of the desired nominal frequency of the skew-corrected clock signal, and a divide-by-K circuit which is reset once every horizontal line. In accordance with another aspect of this invention, the state of the divide-by-K circuit is captured and saved for use in a chroma demodulation apparatus just before it is reset.

Abstract: A defect corrector for a solid-state imager having a number of defective pixels less than the total number of pixels in the imager in which only defect correction signals associated with the defective pixels are generated. The defect correction signals are then combined with photoresponse signals from the corresponding defective pixels, so as to provide a defect compensated photoresponse signal for each of the defective pixels.

Abstract: A solid-state color imaging apparatus comprising a beamsplitter for splitting an incoming light beam representative of an image into at least first and second light beams corresponding to a first color band (e.g., green) of the incoming light and the first color band and a second color band (e.g., blue) of the incoming light, respectively, and first and second solid-state imagers disposed for receiving respective ones of the light beams. The first imager is optically offset with respect to the second imager and their output signals processed so as to develop an apparently improved resolution signal for light of said first color band when compared to the signal developed for light of said second color band.

Abstract: A defect corrector for a solid-state imager in which temperature tracking defect correction signals associated with the defective pixels are generated. The temperature tracking defect correction signals are combined with photoresponse signals from the corresponding defective pixels to provide defect compensation for the photoresponse signal developed from each of the defective pixels.

Abstract: A color television camera including a selectively removable infrared (IR) rejection filter and controllable weighting luminance signal matrixing circuitry features increased low-light sensitity. During low-light conditions, the infrared rejection filter is removed from the optical path of the camera, permitting infrared light to pass to the camera's imaging means; the weighting of the controllable weighting luminance signal matrixing circuitry is altered to provide a more accurate visual representation; and the color subcarrier signal is disabled so that the camera produces only a black-and-white signal.

Abstract: Charge transfer devices typically include a periodically reset floating element output stage coupled to an FET amplifier for sensing the transferred charges. For reducing both low-frequency l/f noise and high-frequency reset noise, the duty factor of the device clocking signals and the reset signal are picked so that at a selected multiple of the clock signal repetition rate, the information component is in phase quadrature with the reset noise component. The charge transfer device output signal is then synchronously detected with a reference signal which is in phase with the selected multiple of the information component.

Abstract: First and second output signals are taken from a floating element in a CCD charge transfer channel and from the terminal drain diffusion of that CCD charge transfer channel. The floating element is part of an electrometer, and the electrometer response is wide-band sampled at the CCD charge transfer channel clocking rate. Current flow through the terminal drain diffusion is sensed by the input circuit of a low l/f noise transresistance amplifier. Continuous-frequency-spectrum low-noise output signal is generated from the low-frequency components of the transresistance amplifier response and from the high-frequency components of the processed second output signal. Subsequent filtering removes unwanted clock and aliased frequency components.

Abstract: A CCD delay line may be tapped using a floating-diffusion electrometer at the tap. Charge sensing is made non-destructive by not resetting the floating diffusion to a reset drain after charge sensing. The resulting charge integration on the floating diffusion causes a smearing of the samples described by successive charge packets. The smearing is in the baseband frequencies of the sample frequency spectrum, but does not appreciably affect the subspectra surrounding harmonics of the delay line clock rate. Consequently, smear-free response to the floating-gate electrometer output signals can be obtained by synchronously detecting them at a harmonic of the delay line clock rate. Using floating-diffusion electrometers, rather than floating-gate electrometers, to sense charge packet amplitudes at taps along a CCD delay line lowers the noise in the output response of output-weighted, charge-coupled-devive transversal fiters.

Abstract: Significant reductions in transfer smear for charge sweep device imagers is made possible by performing the charge sweep operation during only the line retrace period of the operating cycle of the imager. Complete elimination of transfer smear is then possible by using an optical means for blocking the imager from incident illumination during said line retrace periods.

Abstract: Back-illuminated CCD imagers of interline transfer type are made possible by deep, highly doped implant regions which bury the CCDs with respect to the back-illuminated surfaces of the imager substrates. Transfer smear caused by photoconversion in the CCD charge transfer channels must be suppressed in certain of these back-illuminated CCD imagers of interline transfer type, and suitable suppression methods are described.

Abstract: The parallelly arranged charge transfer channels in the image register of a field transfer type CCD imager are clocked with a number of phases equal to 2m, m being a positive integer equal to two or more, during image transfer. The successive gate electrodes receiving each cycle of successive-in-time clock phases during image transfer are considered to be consecutively ordinally numbered first through 2m.sup.th. During the image integration times of odd fields, the first gate electrode in each cycle of the image register is biased to induce a potential energy barrier thereunder, and photoresponse charge is collected under the gate electrodes of the image register exclusive of each first gate electrode. During the integration times of even fields, the (m+1).sup.th gate electrode in each gate-electrode cycle of the image register is biased to induce a potential energy barrier thereunder, and photoresponse charge is collected under the gate electrodes of the image register exclusive of each (m+1).sup.