Abstract: An improved PC system that includes a main CPU microprocessor, a file-based operating system, and a DSP microprocessor arranged so that the DSP can execute main CPU operations during time intervals in which the main CPU is otherwise occupied, thereby increasing the bandwidth of the system is provided. This PC system may include multiple CPUs and/or multiple DSPs.

Abstract: A microprocessor (5) including a plurality of arithmetic logic units (42) is disclosed. At least one of the arithmetic logic units (42) includes a shifter circuit (50) for executing logical and arithmetic shift, rotate, and rotate-through-carry instructions in both the left and right directions, on data words of various lengths. The shifter (50) includes a series of input multiplexers (72, 74, 76, 78) for presenting the data word, carry bits, and extended sign bits to a first funnel shifter stage (80). Each of the multiplexers (72, 74, 76, 78) and first funnel shifter stage (80) are preferably realized by AND-OR-INVERT logic, to allow for 0 logic states and don't cares to be presented by the nonassertion of a control signal thereto. The shifter (50) is implemented as a right funnel shifter, with left shifts and rotates performed by presentation of the data word to the most significant bits of the first funnel shifter stage (80), followed by a right shift of the logical complement of the shift count.

Abstract: An integrated circuit (110) includes, on a single chip, distinct supply voltage terminals and internal on-chip supply conductors connected respectively thereto, including a ground terminal (GND) and terminals for first and second supply voltages (VCC3, VCC5), and a terminal for a selectable supply voltage (VCCDK) and also has a power-good terminal (PWRGOOD5). A plurality of peripheral control circuits (910, 938, 932) are connected by an on-chip internal bus (904). The peripheral control circuits (910, 938, 932) connect to different ones of the internal on-chip supply conductors for operation on the first and second supply voltages (VCC3, VCC5), and the selectable supply voltage (VCCDK). Reset circuitry (2390) is provided for at least one of the peripheral control circuits. A control latch (PMU.sub.-- CNTRL) has a bit (VCCDRV5V) to which the reset circuitry (2390) is responsive.

Abstract: A computer system (6) includes a printed circuit board (302), a microprocessor chip (102), a peripheral unit chip (110), a card interface chip (112), and a display controller chip (114) mounted on the printed circuit board (302) at vertices of a quadrilateral (303). A clock buffer chip (180) is mounted on the printed circuit board (302) in the interior of the quadrilateral (303) and connected to each of the microprocessor chip (102), peripheral unit chip (110), card interface chip (112), and display controller chip (114). Other circuits, systems, and methods are disclosed.

Abstract: A single-chip integrated circuit device (110) includes an on-chip bus (904) and a plurality of integrated circuit functional blocks (934, 932) having respective clock inputs connected to the on-chip bus (904). An address decoder (in 1210) is provided responsive to particular addresses to supply an output of a differing character (IDE/NON-IDE) depending on whether or not the particular addresses are received. A clock generating circuit (1201) having a control input (IDE/NON-IDE) fed by the output of the address decoder (in 1210) and a clock output (SYSCLK) connected to the on-chip bus (904) supplies a clock signal that depends in rate on whether or not the particular addresses are received. Other circuits, systems, and methods are disclosed.

Abstract: An integrated circuit includes a single chip (102) that has a microprocessor (702), a memory controller unit (718), an internal bus (714) connecting the microprocessor (702) and the memory controller unit (718), and an external bus to internal bus interface circuit (716). The microprocessor (102) occupies a substantially rectangular region on a substrate (802). The memory controller unit (718) occupies a first strip along one side of the microprocessor unit (702) accessible via the bond pads broadside to the first strip. Other circuits, systems, and methods are disclosed.

Abstract: An electronic system for use with a host computer. The system includes electronic circuitry including a first semiconductor chip generally operable for a first function and also adapted for input and output of emulation signals. This is combined with emulation circuitry including a second semiconductor chip adapted for connection to the host computer. The emulation circuitry is connected to the electronic circuitry to generate emulation signals to input to the electronic circuitry and to accept emulation signals from the electronic circuitry. A physical assembly supports the emulation circuitry and the electronic circuitry as a unit. Other electronic systems and emulation and testing devices, cables, systems and methods are also disclosed.

Abstract: A method of using a computer to assemble source code having a number of sub-instructions on each source code line, such that a processor may execute more than one sub-instruction during a single clock cycle. The computer is used to assign a binary conflict mask to each sub-instruction and to compare these conflict masks to determine whether a conflict exists among the sub-instructions. Additional features of the invention are determining the nature of the conflict and generating an appropriate indication signal to the user.

Abstract: A data processing device comprising a clock generator for producing pulses establishing instruction cycles, a memory accessible by assertion of addresses, an instruction decode and control unit, having an instruction register operative to hold a program instruction, operative to decode a program instruction providing control signals according to a pipeline organization to control the operations of the data processing device within each instruction cycle and to initiate a block sequence responsive to an instruction code representing a block instruction. A program sequencer circuit, having a program register to hold a program count corresponding to a program address, is operative to access the memory with the contents of the program register to obtain the program instruction corresponding to the program address.

Abstract: An apparatus and method for maintaining variable data in a non-volatile electronic memory device comprises a shifter array (106) which provides a shifter value to shifter register (104). Shifter register (104) uses 8-bit column decoder (110) to specify which of a plurality of overlapping storage units in array (94) will store variable data provided from register (92). Address register (112) specifies to row decoder (116) which of two rows in shifter array (106), pointer array (118) and array (94) will be accessed by read and write operations. Pointer array (118) stores an index specifying which of the two rows contains the most recently updated variable data. Shifter register (104) uses 8-bit column decoder (108) to specify which of a plurality of adjacent storage units in pointer array (118) will store the index. OR gate (98) specifies when to replace an overlapping storage unit in array (94) and an adjacent storage unit in pointer array (118).

Abstract: An integrated circuit buffer includes a source follower output transistor having an output and also connected by a voltage dropping circuit to a supply rail thereby introducing a controlled amount of Miller effect capacitance in the source follower output transistor. The buffer also has a common source output transistor and a unidirectional conducting circuit connecting between the common source output transistor and the source follower output transistor. Other buffers, palette devices, computer graphics systems and methods are also disclosed.

Abstract: An emulation device including a serial scan testability interface having at least first and second scan paths, and state machine circuitry connected and responsive to said second scan path generally operable for emulation control of logical circuitry associated with said emulation device.

Abstract: A method is provided for deinterlacing pixels in a video display system operable to display images as a plurality of pixels arranged in first and second fields of interlaced rows, at least one video component level quantified by a numerical video component value characterizing each pixel in an image with the video component levels for the pixels in the first and second fields being updated on alternate scans. A global mean video component value is computed from the video component values generated for a previous scan of at least one of the first and second fields. A global standard deviation is computed for the global mean. A local mean video component value is computed from the video component values generated for a plurality of pixels being updated as part of the current scan of the first field and defining a neighborhood of a pixel in the second field being deinterlaced. A local standard deviation is computed form the local mean video component value.

Abstract: A synchronous vector processor SVP device having a plurality of one-bit processor elements organized in a linear array. The processor elements are all controlled in common by a sequencer, a state machine or a control circuit (controller) to enable operation as a parallel processing device. Each processor element includes a set of input registers, two sets of register files, a set of working registers, an arithmetic logic unit including a one-bit full adder/subtractor, and a set of output registers. In video applications each processor element operates on one pixel of a horizontal scan line and the SVP is capable of real-time digital processing of video signals. In video applications a data input control circuit including a master controller circuit, a vertical timing generator circuit, a constant generator circuit, a horizontal timing generator circuit and an instruction generator circuit is provided.

Abstract: A memory cell constructed in accordance with the present invention includes a node operable to present an electrical level representing a first state or a second state. Further included is a first switching device having a first terminal connected to the node such that if the first switching device were to close, the electrical level at the node would be connected to a second terminal of the first switching device. Additionally, second and third switching devices are provided both having first and second terminals and both operable to switch as a function of the state at the node. Finally, a single control switching device is provided in association with the second and third switching devices wherein a control signal switches the control switching device such that the state at the node may be determined by connecting to the first terminals of the second and third switching devices.

Abstract: An integrated circuit has a semiconductor die with a substrate and at least first and second bond pads. An internal circuit is fabricated on the semiconductor die and connected to the first bond pad. An electrostatic discharge protection circuit including cascaded bipolar transistors is connected in series with a field effect transistor between the first and second bond pads. In another version, an output buffer of the integrated circuit is divided into sections. An electrostatic discharge protection circuit is triggerable in response to a voltage in the substrate. Resistive connections are provided from the sections of the output buffer to one of the bond pads. The output buffer is operative upon an electrostatic discharge event to inject sufficient charge into the substrate to produce the voltage to trigger the electrostatic discharge protection circuit. Other circuits, devices, systems and methods are also disclosed.

Abstract: A palette device responsive to color codes supplied on a bus and for producing signals representing color for a color display device. The palette device includes a plurality of look-up table memories each for supplying color data words in response to color codes supplied to access the memories respectively and a plurality of digital to analog converters respectively connected to said plurality of look-up table memories and responsive to the respective color data words from the memories to produce a plurality of analog color signals. A splitter circuit is provided for connection to the bus and is connected at a plurality of outputs thereof to access each of the look-up table memories concurrently. Other palette devices, computer graphics systems, facsimile systems, printer systems and methods are also disclosed.

Abstract: An integrated circuit has a clock input pad and circuitry operative in response to a clock signal. Clock transitions at the clock input pad are potentially subject to glitches due to noise and ringing. Further provided is a glitch remover circuit having a logic gate having first and second inputs. The glitch remover circuit has a series of circuits coupled to the clock input pad with differing delays for positive edges than for negative edges. The series of circuits has an output connected to the first input of the logic gate, with the second input coupled to the series of circuits intermediately. Other devices, systems and methods are also disclosed.

Abstract: A data processing device includes an electronic processor responsive to a context signal and operable in alternative processing contexts identified by the context signal. First and second registers are connected to the electronic processor to participate in one processing context while retaining information from another processing context until a return thereto. A context switching circuit is connected to the first and second registers and operates to selectively control input and output operations of the registers to and from the electronic processor depending on the processing context. Other devices, systems and methods are also disclosed.

Abstract: A microprocessor, specially adapted for graphics processing applications, and which has a self-emulation capability by which the contents of its internal registers may be dumped or loaded to or from external memory on an instruction-by-instruction basis, is disclosed. The microprocessor has circuitry which is responsive to an emulate enable signal, or to a predetermined instruction code, so that normal execution is halted at the end of the ion, with execution jumping to a predetermined vector. Responsive to a dump signal, the microprocessor begins execution of a routine which presents a predetermined series of memory addresses on a memory bus, in conjunction with the contents of registers internal to the microprocessor. Accordingly, the addressed locations of a memory device connected to the memory bus can be written with the register contents, for subsequent interrogation by the user.