Abstract: An erasable, programmable ROM (10) with three redundant bit-cell arrays (10A, 10B, 10C) includes an error-flagging circuit (30) that detects bit-cell failures and provides notification of each such failure. The error-flagging circuit (30) includes a plurality of XOR gates (32), each receiving the corresponding redundant data bits for one of the bits of an addressed byte, and a NOR gate (36) which receives the outputs from each of the XOR gates (32). Each XOR gate detects when the logic states for the input redundant bits are not identical, indicating a bit-cell failure has occurred, and provides a corresponding logic state output. The NOR gate (36) detects when any of the XOR gates (32) has indicated a bit-cell failure, and generates an error-flag output providing notification of such failure.

Abstract: An elastic buffer for absorbing frequency jitter or drift of an incoming data signal which includes a serial stack of data registers. These data registers are used for storing data bits from an incoming data stream one at a time with each bit adjacent a next earlier bit at a frequency equal to the frequency of the incoming data and also for releasing stored bits onto an output data line. The stored bits are released one at a time at a predetermined fixed rate equal to the average frequency of incoming data from a number of registers away from the register into which data is being written which depends on the frequency difference between incoming data and the fixed rate aforesaid.

Abstract: An adapter for modifying graphics software programs at load time. The invention is a process, which may be part of a hardware or firmware configuration used with a computer system, and which scans the program for selected instructions representing routines to be replaced with a substitute routine. If such an instruction is encountered, the instruction is replaced with an interrupt trap. The substitute graphics routine is located at an address stored at the interrupt trap location.

Abstract: A passive interface between a processor and a peripheral device is shown. The peripheral device could also be another processor. The interface allows asynchronous communication between the devices. Speed limitations are minimized as the processor has the ability within the interface to know when it can send data, and when it has received data. The number of interface pins is also minimized. Also, communication between devices can still be performed even if the devices have different data bus widths.

Abstract: A processor which has two different communications modes, a test mode, an an emulator mode is shown. These modes are selected by controlling inputs to two pins. More modes could be added with more pins. When a given mode is switched into, certain I/O pins instantly change function. Minimal hardware and software is required to implement a switch thus allowing rapid switches.

Abstract: A microcomputer is disclosed which is specifically designed for computation-intensive applications. The microcomputer contains on-chip RAM and ROM, and has peripheral ports for access of external memory and input/output functions. The microcomputer has a central processing unit with a floating-point multiplier in parallel with an arithmetic logic unit, and uses a plurality of registers as multiple accumulators. The central processing unit further contains two auxiliary arithmetic logic units, in parallel with one another, and which are each connected to a set address lines in a memory bus; the two auxiliary arithmetic logic units thus generate two separate memory addresses in parallel. The memory bus also contains one set of data lines, connected to the RAM and ROM, and to the central processing unit. The on-chip RAM and ROM are responsive to the two sets of address lines in time-multiplexed fashion to provide memory access via data lines twice per system clock cycle.

Abstract: There is disclosed a system and method for demodulating an analog signal using digital conversion of the analog signal. In one embodiment the incoming modulated signal is digitally sampled and a calculation is made as to both the short term and long term energy of the digitized version of the analog signal. The deviation between the short and long term energy levels is used to determine the amount of modulation of the incoming analog signal. An analog demodulated signal is then reconstructed from the digitized deviation calculations. In an alternate embodiment, a digital signal processor is used to derive the demodulated signal.

Abstract: A television receiving system includes a digital unit, which has at least one single-instruction multiple-data processor, especially suited for television processing. The processor receives data samples of each horizontal line word-serially, but processes the line in parallel. The processor has input, computational, and output layers that operate concurrently. Internal register files emulate line memory to eliminate the need for external line memories. The processor may be programmed with various improved definition television tasks, downloaded to it from a host development system.

Abstract: A television receiving system includes a digital unit, which has at least one single-instruction multiple-data processor, especially suited for television processing. The processor receives data samples of each horizontal line word-serially, but processes the line in parallel. The processor has input, computational, and output layers that operate concurrently. Internal register files emulate line memory to eliminate the need for external line memories. The processor may be programmed with various improved definition television tasks, downloaded to it from a host development system. Field memories and multiplexers control the data flow so that a sub-picture and a full size picture may be displayed at one time.

Abstract: A television receiving system includes a digital unit, which has at least one single-instruction multiple-data processor, especially suitable for television processing. The processor receives data samples fo each horizontal line word-serially, but processes the line in parallel. The processor has input, computational, and output layers that operate concurrently. Internal register files emulate line memory to eliminate the need for external line memories. The processor may be programmed with various improved definition television tasks, downloaded to it from a host development system. Field memories and multiplexers control the data flow so that a still picture may be displayed.

Abstract: A data processing device includes an instruction decoder and an arithmetic logic unit having first and second inputs and an output. An accumulator is connected between the output and first input of the arithmetic logic unit. A further register is connected between the accumulator and the second input of the arithmetic logic unit. The arithmetic logic unit includes circuitry for computing a digital value to the accumulator as well as an additional circuit. The additional circuit thereupon compares the value at the second input from said register with the digital value in the accumulator in response to a command from the instruction decoder and then stores to the register the lesser or the greater in value of the contents of the register and the digital value in the accumulator depending on the command. Other devices, systems and methods are also disclosed.

Abstract: A clock stability circuit (10, 20, 30, 40) assures stable clock generator operation after oscillator start-up, such as during re-entry after a low-power Halt mode in a microprocessor or microcomputer. The clock stability circuit detects stable clock cycles that transition between a selected high amplitude threshold (near VDD) and a selected low amplitude threshold (near VSS), and provides a clock stable signal after a selected number of stable clock cycles, indicating that the oscillator has stabilized. The clock stability circuit includes four modules: input sampler (10), pulse generator (20), pulse counter (30) and control logic (40). The input sampler module includes CMOS NAND gates (11, 14) respectively fabricated with p/n-channel ratios to provide a CLOCK A signal that transitions at the selected high amplitude threshold of an oscillator cycle, and a CLOCK B signal that transitions at the selected low amplitude threshold.

Abstract: A microcomputer is disclosed which has an architecture designed for the efficient performance of digital signal processing applications. The microcomputer contains a primary arithmetic logic unit for performing data operations, and a pair of auxiliary arithmetic logic units for calculating indirect memory address values. A memory bus within the microcomputer has data lines therein, and two sets of address lines; each of the auxiliary arithmetic logic units is connected to one of the sets of address lines. The auxiliary arithmetic logic units are capable of performing circular addressing calculations, by calculating the next memory address from the prior memory address and an index value, and by comparing the next memory address to the limits of the memory block within the circular addressing scheme.

Abstract: A test circuit for a logic device having ports. The test circuit includes a serial scan path for serially transferring externally generated test vectors from a serial test input to a serial test output. A storing circuit stores a data bit and has a node at which the data bit is stored. A first interface circuit interfaces the node with a first one of the ports for synchronous transfer of data from the logic device to the node. A second interface circuit interfaces the node with the serial scan path to tranbsfer data from the serial scan path to the node. A coupling circuit connects the storing circuit to a second of the ports to transfer a logic level responsive to the data bit to the logic device during test. Also the coupling circuit temporarily couples the data bit from the node to the serial scan path also during test.

Abstract: A graphics coprocessor designed to work in conjunction with a host graphic processor in a graphics system. The coprocessor is adapted to perform arithmetic calculations including matrix calculations. The matrix size is such that the intermediate results require more registers than are practical to include in the coprocessor. This has been solved by arranging for certain selected ones of the intermediate results to continue within the program execution from stage to stage and avoiding intermediate storage.

Abstract: The disclosure relates to an electrical connection between a bonding pad on a semiconductor chip and a wire wherein the bonding pad is formed of copper doped aluminum and the wire is formed of copper doped gold. The wire has from about 100 to about 10,000 parts per million copper and the pad has from about 5000 to about 50,000 parts per million copper.

Abstract: A microcomputer is disclosed which provides for a dedicated DMA data and address bus connecting an on-chip DNA controller with on-chip memories, and with on-chip ports for access to external memory and input/output devices. The DMA controller contains a control register which has two start bits, capable of representing four start codes. The four start codes allow for the unconditional starting and aborting of a DMA transfer, as well as for stopping the DMA after the current read or write operation, or after the next write operation (i.e., completion of a data word transfer). The control register also contains two status bits which the DMA controller writes with the status of the DMA operation, and also contains two synchronization bits for synchronizing the DMA operation in the source, destination, or source and destination modes (or not at all). Two interrupt enable registers are provided in the microcomputer, for independently enabling interrupts for the CPU and the DMA.

Abstract: A microcomputer is disclosed which has an architecture designed for the efficient performance of digital signal processing applications. The microcomputer contains a primary arithmetic logic unit for performing data operations, and a pair of auxiliary arithmetic logic units for calculating indirect memory address values. A memory bus within the microcomputer has data lines therein, and two sets of address lines; each of the auxiliary arithmetic logic units is connected to one of the sets of address lines. The auxiliary arithmetic logic units are capable of performing circular addressing calculations, by calculating the next memory address from the prior memory address and an index value, and by comparing the next memory address to the limits of the memory block within the circular addressing scheme.

Abstract: A grasping arm subassembly article has an inner arm pivoted to a frame with an outer arm pivoted between its ends to the inner arm. The outer arm is pivotally moved graspingly in response to pivotal movement of the inner arm by a linkage mechanism including serially pivoted first, middle, and second links. The second link is pivoted to the outer arm and the first link is pivoted to the frame. Advantageously, the middle link is pivoted to the inner arm at a point between its own ends and between the ends of the inner arm. A hydraulic cylinder is pivoted to the frame and to the arm subassembly for powering the arm.A grasping device suitably uses two or more such arm subassemblies movable inwardly and outwardly about the frame. In a specific example of a refuse container collection function, the grasping is done by a collection vehicle. The device for grasping the containers comprises a telescopically extensible boom assembly adapted to be mounted to the chassis frame of the vehicle.