Abstract: An interactive video system employs Motion Picture Expert Group (MPEG) video compression to transfer images from a remote server to a television. The images correspond to dialog frames in a graphical user interface. During an authoring process, the dialog frames are created by first creating a background image and then adding foreground elements, such as buttons. A set of MPEG video frames is created by encoding the resulting images according to the MPEG algorithm. The MPEG video frames are delivered to the television in sequence, where an MPEG decoder uses them to reconstruct the dialog images that are subsequently displayed. The system also contains an object-oriented database that maintains the necessary MPEG file ordering and also carries out menu navigation commands received from the user. The object classes include NODE, BRANCH, and DISPLAY. NODE objects correspond to dialog frames, and BRANCH objects correspond to user-selectable features such as buttons.

Abstract: An equipment cabinet employs a rack-mountable equipment enclosure surrounded by a base, a cap, and front and rear covers. Each cover consists of a bezel and a door reversibly mounted thereon via removable hinge pins. The bezels have sidewalls that rest against ledges on the edges of the enclosure to receive support therefrom. The door has a centrally-located latch, the latch having a pawl with an eccentric catch portion that engages a latch opening on a ledge extending from the bezel. The pawl also has a tab that rests between the ends of an arcuate raised portion on the rear of the door to limit the rotational travel of the pawl.

Abstract: Threshold optimization for SOI transistors is achieved through the formation of a layer of positive charge within the gate to correspond to the positive polarity formed in the substrate by ion implantation for threshold voltage control. A positive charge layer is formed by furnishing sulfur ions on the substrate before growth of an oxide to form a portion of the gate oxide. The sulfur will form a charge layer on the surface of the oxide, and an additional oxide is then deposited on the same to form the gate oxide as a sandwich with the positive charge layer in the same.

Abstract: A read buffering system employs a bank of FIFOs to hold sequential read data for a number of data streams being fetched by a computer. The FIFOs are located in the memory controller, so the system bus is not used in memory accesses used to fill the stream buffer. The system stores addresses used for read requests made by a CPU, and if a next sequential address is then detected in a subsequent read request, this is designated to be a stream (i.e., sequential reads). When a stream is thus detected, data is fetched from DRAM memory for addresses following the sequential address, and this prefetched data is stored in one of the FIFOs. The system also prevents the unnecessary prefetching of data by preventing certain CPU requests from being used to detect streams. A FIFO is selected using a least-recently-used algorithm. When the CPU subsequently makes a read request for data in a FIFO, this data can be returned without making a memory access.

Abstract: Threshold optimization for SOI transistors is achieved through the formation of a layer of charge within the gate oxide, which layer has a polarity corresponding to that of the ion implantation for threshold voltage control. A negative charge layer is formed by furnishing trace amounts of aluminum on the substrate before growth of an oxide to form a portion of the gate oxide. The aluminum will form a charge layer on the surface of the oxide and an additional oxide is then deposited on the same to form the gate oxide as a sandwich with the charge layer in the same.

Abstract: A peak detector for use in a fiber optic receiver has a capacitor, an input amplifier driving the capacitor, and a feedback differential amplifier coupled between the capacitor and an input of the input amplifier. The input amplifier is a complementary buffer with unity gain modified to include an additional transistor on one rail that receives an inverter voltage generated by the differential amplifier. The inverter voltage equals the difference between twice the capacitor voltage and an input voltage applied to the peak detector. The input amplifier in a positive peak detector functions so that the capacitor voltage tracks the input voltage when it exceeds the inverter voltage, and equals the average of the input voltage and inverter voltage when the input voltage is less than the inverter voltage. A negative peak detector operates similarly but with opposite polarity. The peak detector also contains transistors used to reset the capacitor voltage upon assertion of a reset signal.

Abstract: A peak detector for use in a fiber optic receiver has a capacitor, an input amplifier driving the capacitor, and a feedback differential amplifier coupled between the capacitor and an input of the input amplifier. The input amplifier is a complementary buffer with unity gain modified to include an additional transistor on one rail that receives an inverter voltage generated by the differential amplifier. The inverter voltage equals the difference between twice the capacitor voltage and an input voltage applied to the peak detector. The input amplifier in a positive peak detector functions so that the capacitor voltage tracks the input voltage when it exceeds the inverter voltage, and equals the average of the input voltage and inverter voltage when the input voltage is less than the inverter voltage. A negative peak detector operates similarly but with opposite polarity. The peak detector also contains transistors used to reset the capacitor voltage upon assertion of a reset signal.

Abstract: A single Reed-Solomon code is employed with modifications to allow information systems the freedom of selecting redundancy from 1 to R symbols, where R is the number of redundant symbols that the unmodified Reed-Solomon code employs. If P is the number of discarded redundancy symbols, then R-P redundancy symbols are retained, and the minimum distance of the modified code is 1+R-P. The system uses one of several alternative decoding schemes. One general scheme employs error-and-erasure decoding, and treats the P deleted symbols as erasures. Another general scheme operates directly on the shortened, modified code-word and modifies both the error syndromes and the error information derived from the syndromes to compensate for the deleted symbols.

Abstract: A method and apparatus for identifying and synchronizing to two different fields in a disk drive employs different synchronization or "sync" patterns to reduce the chances of mis-identifying and false-identifying a field. Two very distinct synchronization patterns have been found that satisfy the d=1, k=7 run-length constraints of a data code used in the disk drive. During operation, one sync pattern is searched for to identify and synchronize to its associated field, then the field itself is read. This procedure is then repeated for the other sync pattern and its associated field. Also, the phase of a preamble preceding each sync character is established, so that the number of comparisons needed to find either sync character is reduced. A sync detector operates on cell pairs, and has a selector that selects which sync pattern to search for. The sync detector also has special features that enable it to find preamble and DC Erase fields in the disk cell stream.

Abstract: A staged CMOS output buffer has multiple output transistors connected in parallel and driven by corresponding predrivers. Each predriver has a first input from which an inactive output transistor can be turned on, and a second input from which the other, active output transistor can be turned off. The input to the output buffer is coupled directly to the second input of both predrivers to turn the output transistors off when switching begins, and a resistor-capacitor (RC) circuit is inserted between the first inputs to stagger the predriver turn-on times to reduce the peak and slope of the switching current. The predriver employs chains of pass transistors to achieve both tri-state functionality and the simultaneous turn-off necessary for the staged configuration. A split termination is also employed to reduce switching current, especially NMOS-PMOS crossover current.

Abstract: A thin film magnetic head, and process for making the same, features a thin film magnetic transducer formed from multiple layers of film and having a magnetic yoke interacting with an electrical coil. The yoke has multiple magnetic flux circuits, deposited on multiple layers of film, encircling the center of the transducer and connected together by proximal and distal vias. A coil has multiple turns intertwined with the yoke, passing between the distal and proximal vias so that the distal vias are exterior to the coil and the proximal Vias are interior to the coil, to provide at least four magnetic flux interactions between the coil and the yoke. In preferred embodiments at least one layer of the film is deposited with at least two pole pieces having different easy axis orientations.

Abstract: A duplicate address condition in a computer network may be detected by a station of the type for attachment to a computer communications network, the network capable of maintaining communications among a plurality of stations, the station having means for receiving a frame, the frame having a source address field and a frame control field; means for maintaining an individual address of the station; means for maintaining a source address list of address, the source address list not containing the individual address; means for determining that a contents of the source address field in the frame matches at least one address in the source address list; means for determining that the frame control field of the frame has a predetermined contents; and, means, responsive to the source address of the frame matching at least one address in the source address list and the frame control field of the frame having the predetermined value, for setting an indicator that a duplicate address condition exists.

Abstract: A method of data recovery in systems employing error-correction coding techniques is described. The technique may be used, for example, in conjunction with a data storage device or a data communications network. Several trials of accessing or transmitting the ECC-protected data are performed. The data from each trial is decoded, and is also saved. If none of the trials results in the successful decoding of the data, then a reconstruction function is employed to create a reconstructed version of the data from the sequence of data created by the trials. One method of reconstruction involves majority voting on a symbol-by-symbol basis. The reconstructed data created that way is then decoded in the same fashion as for each trial. A more powerful reconstruction function employs a threshold to determine whether each voted-on symbol is sufficiently "reliable". If not, it is marked as an erasure.

Abstract: A method and apparatus for polling a status register selectively delays the returning of status data in the status register. Prior to polling, a match register is loaded via a system bus with a desired status. Status data is presented to the system bus when the status data is the same as the desired status. The features of the invention also permit the masking of selective bits of the status register during the comparison of the status data with the desired status. A mode register selectively inhibits the delayed presentation, and a timer ensures that status data is presented to the system bus within a predetermined interval even if the status data is not the same as the desired status.

Abstract: A method and apparatus for optimizing the track seeking operation of disc drives by adaptively changing the seek velocity profile in response to the actual performance of the drive during track seeking operations based upon the amount of head overshoot and the actuator power dissipation.

Abstract: An computer assembly having an integral video display and processor subsystem in a single enclosure is described. The assembly contains an electrically conductive safety wall inside the enclosure which separates the interior of the enclosure into a high-voltage region where the video display components are mounted, and a low-voltage region where the processor subsystem is mounted. The enclosure has a removable rear cover which allows access to the processor subsystem for upgrading memory. An electrically conductive liner is attached to the rear cover for EMI shielding of the low-voltage region.

Abstract: A new expert system performs a redesign in connection with an original design. The expert system comprises a discrepancy determination component that identifies a discrepancy between operation of the original design and a desired operation. A redesign component including at least one redesign module associated with a discrepancy generates a redesign in response to the original design and the identified discrepancy. Finally, a redesign generation component generates a redesign module in response to a previously-identified discrepancy and design, the redesign module thereafter being used by the redesign component.

Abstract: A data storage system having a number of disk drives is disclosed. Each disk drive is provided with a disk spindle driven by a spindle motor. The disk spindle is utilized for mounting one or more disks whose surface is used for data storage. A read/write head mounted on an actuator is provided for each disk surface. Each read/write head is positioned over a desired location on the disk surface by a control mechanism in order to transfer data to and from the disk surface. Data and position information are encoded on each disk surface according to a pre-specified format. The rotation of the disk spindle is controlled to maintain a desired angular position and velocity. A sensor signal indicative of the disk spindle angular position and velocity is obtained independently of the position information encoded on the disk surface. A reference signal, which is obtained from the disk surface, is combined with the sensor signal to adjust the angular position of the disk spindle.

Abstract: A CPU module has a processor, cache memory, cache controller, and system interface attached to a processor bus. The system interface is attached to a system bus shared by memory, I/O, and other CPU modules. The cache controller requests control of the processor bus from the processor, and grants control to the system interface. The system interface uses the processor bus to store fill data obtained from memory into the cache in response to a read miss. The system interface also monitors system bus traffic and forwards the addresses of cache blocks to be invalidated to the cache controller over an invalidate bus. The cache controller requests control of the processor bus during a read miss to perform invalidates and writebacks. The processor grants control to the cache controller before the read miss completes, enabling the cache controller to proceed, and then re-issues the read.

Abstract: A disk in a disk drive has radial spokes wherein servo bursts are recorded, and multiple concentric bands holding data blocks in pre-defined block frames. To maximize data density, the data rate in each band is proportional to the band radius, and the ratio of block frames to spokes in a given band may be non-integral. In such bands, some data blocks are split by a spoke. A disk controller in the disk drive uses a byte position accumulator (BPA) when splitting a data block. During the transfer of a data block, the BPA counts at the nominal data transfer rate to continually identify by its position in the data block a byte therein to be transferred shortly. The BPA output feeds a latch which is normally open to receive the BPA output. A timer within the disk controller establishes the rotational time at which the data transfer must be suspended to avoid a spoke. The timer generates an early warning signal in advance of this time which closes the latch.