Abstract: An architecture, module set and platform to provide total power protection from utility disturbances. Power supplies employing the invention are built on power buses for utility AC input, battery DC input and conditioned AC output housed in the platform and employ modular line-to-AC-or-DC power-factor-correcting converters and battery/charger sets either housed in the platform or integrated as part of the front end power supply for a critical load such as a computer.

Abstract: A selective multilevel caching method and system including a main memory and a plurality of cache memories are disclosed. The main memory and cache memories are arranged in a multilevel hierarchy: the main memory is at the lowest hierarchical level; the cache memory that is coupled directly to the central processing unit (CPU) is at the highest hierarchical level; and the remaining cache memories are coupled in the hierarchy at intermediate hierarchical levels therebetween. Each hierarchical level contains cache logic as well as a cache memory. Each cache logic responds to a cache level code that is associated with an address specified in each CPU read or write data request. The cache level code specifies the highest hierarchical level at which data associated with the data request may be written. Each cache logic uses the cache level code to determine if data will be written to the cache memory at the same hierarchical level as that cache logic. Each CPU write request further includes a cache control code.

Abstract: In a method and system for dynamically improving the performance of a server in a network, a tuning system monitors a workload of the server in real time, monitors a set of internal performance characteristics of the server in real time, and monitors a set of adjustable server parameters of the server in real time. The workload of the server may include the frequency and type of service requests received by the server from clients in the network. The internal server performance characteristics may include, for example, a data cache hit ratio of a data cache in the server. The set of server parameters may include, for example, the overall data cache size or the data cache geometry of the server. The tuning system periodically alters one or more of the set of adjustable server parameters as a function of the workload and internal performance characteristics of the server.

Abstract: A read buffering system and method employs a bank of FIFOs to hold sequential read data for a number of data streams being fetched by a computer. The FIFOs are located in the memory controller, so the system bus is not used in the memory accesses needed to fill the stream buffer. The buffer system stores addresses used for read requests made by a CPU, and if a next sequential address is then detected in a subsequent read request, this is designated to be a stream (i.e., sequential reads). When a stream is thus detected, data is fetched from DRAM memory for addresses following the sequential address, and this prefetched data is stored in one of the FIFOs. A FIFO is selected using a least-recently-used algorithm. When the CPU subsequently makes a read request for data in a FIFO, this data can be returned without making a memory access, and so the access time seen by the CPU is shorter.

Abstract: A read buffering system employs FIFOs to hold sequential read data for a number of data streams being fetched by a computer. When the system sees a read command from the CPU, it stores an incremented value of the address of the read command in a history buffer and marks the entry as valid. The system detects a stream when a subsequent read command specifies an address that matches the address value stored in the history buffer. Upon detecting a stream, the system fetches data from DRAMs at addresses that follow the address of the subsequent read command, and stores it in a FIFO. However, to reduce unnecessary prefetching, the system looks for a read X, write X, read X+1 (where X and X+1 designate addresses) succession of commands so as to prevent them from creating a stream. This succession occurs often and qualifies as a stream, but is seldom followed by other reads that maintain the stream.

Abstract: A heat dissipating arrangement in a portable computer uses a copper slug disposed between a heat-generating central processing unit (CPU) chip and the underside of a metallic keyboard baseplate. The slug also extends through a copper-plated hole in a printed circuit (PC) board, and is either soldered to the copper plating or press-fit into the hole to enhance heat transfer between the slug and the PC board. Small through-holes extend through the PC board and the copper plating next to the opening. These through-holes connect the copper plating to several layers of etch within the PC board, so that these layers act like fins on a heat sink to increase heat transfer away from the CPU.

Abstract: A data storage system using a RAID array and a logging process and apparatus that identifies a parity block that may not contain the proper parity for its associated data blocks and which prevents such inconsistent parity information from being used in the regeneration of unavailable data. A small fraction of the blocks of each disk are dedicated to storing parity metadata bits. The parity metadata is associated with the parity blocks and identifies whether or not each parity block contains the proper parity information for its associated data blocks or may contain invalid information. The data integrity of the RAID array is preserved by preventing the generation of undetected corrupt data.

Abstract: An interactive video system employs Motion Picture Expert Group (MPEG) video compression to transfer images from a remote server to a television. The images correspond to dialog frames in a graphical user interface. During an authoring process, the dialog frames are created by first creating a background image and then adding foreground elements, such as buttons. A set of MPEG video frames is created by encoding the resulting images according to the MPEG algorithm. The MPEG video frames are delivered to the television in sequence, where an MPEG decoder uses them to reconstruct the dialog images that are subsequently displayed. The system also contains an object-oriented database that maintains the necessary MPEG file ordering and also carries out menu navigation commands received from the user. The object classes include NODE, BRANCH, and DISPLAY. NODE objects correspond to dialog frames, and BRANCH objects correspond to user-selectable features such as buttons.

Abstract: A memory system has a stream buffer with several performance-enhancing features. Two distinct sets of latches receive data from the memory array. One set feeds the stream buffer, while the other holds memory data that is destined for a system bus. The dual-latch configuration allows stream buffer fills to proceed even if system bus stalls prevent the memory data latch from being timely emptied. The memory controller prefetches a number of data blocks depending on the interleave factor of the memory system, as well as in response to control information from the CPU that can override the interleave-based number in some system configurations. The stream buffer employs a history buffer containing the addresses of recently-read memory locations in order to declare a new stream. The addresses of memory reads are normally entered into the history buffer on a round-robin basis.

Abstract: A cache memory refreshment mechanism employing ageing-out criteria to remove stale entries from the cache memory. Entries in the cache memory may have one of four states: 1) VALID, indicating that the entry may be used by the local processor; 2) DYING, indicating that the entry may be used, but that it has been in existence in the cache for a predetermined period of time; 3) REFRESH, following a dying status, indicating a) that the entry may still be used, b) that the entry has just been used while in the dying state, and c) that retrieval of data to update the entry and return it its valid state is being effected; and 4) IDLE, indicating that the entry has been aged out of the cache, and may not be used. The refresh status enables a cache entry may be updated independently of the processor using the cache, and thus the number of processor stalls resulting from data not being available in the cache after having been aged out is substantially reduced.

Abstract: An equipment cabinet employs a rack-mountable equipment enclosure surrounded by a base, a cap, and front and rear covers. Each cover consists of a bezel and a door reversibly mounted thereon via removable hinge pins. The bezels have sidewalls that rest against ledges on the edges of the enclosure to receive support therefrom. The door has a centrally-located latch, the latch having a pawl with an eccentric catch portion that engages a latch opening on a ledge extending from the bezel. The pawl also has a tab that rests between the ends of an arcuate raised portion on the rear of the door to limit the rotational travel of the pawl. The base, cap, and covers are configured so that the enclosure is surrounded by hollows forming a peripheral passageway for cabling and the like. The base and cap have front and rear handle-like projections through which cables may be routed, and the covers have inward-facing snap tabs that engage the handle-like projections to secure the covers to the base and cap.

Abstract: A method of testing a memory containing data being used by a processor uses a dedicated diagnostic test page (DTP) and diagnostic status page (DSP) in the memory under test to carry out the testing. The DTP is address-tested and pattern-tested first. Then, each page of the memory is in turn copied to the DTP, tested, and then restored from the DTP. During the test, the address of the page being tested is stored in the DSP along with a valid flag and an error detection code (EDC). A recovery procedure uses the information on the DSP to restore memory pages if the test is interrupted.

Abstract: A read buffering system employs a bank of FIFOs to hold sequential read data for a number of data streams being fetched by a computer. The FIFOs are located in the memory controller, so the system bus is not used in the memory accesses needed to fill the stream buffer. The buffer system stores addresses used for read requests made by a CPU, and if a next sequential address is then detected in a subsequent read request, this is designated to be a stream (i.e., sequential reads). When a stream is thus detected, data is fetched from DRAM memory for addresses following the sequential address, and this prefetched data is stored in one of the FIFOs. A FIFO is selected using a least-recently-used algorithm. When the CPU subsequently makes a read request for data in a FIFO, this data can be returned without making a memory access, and so the access time seen by the CPU is shorter.

Abstract: Cooperative patterns are formed in stencils and/or substrates that facilitate the monitoring and control of the circuit assembly process. A pattern of successively-larger etch blocks receives a corresponding pattern of same-size solder blocks; solder reflow problems are indicated when either too many or too few etch blocks are completely covered by solder after reflow. A pattern of same-size etch blocks receives a corresponding pattern of successively-larger solder blocks; problems with solder stencil clogging are indicated when smaller ones of the etch blocks do not receive solder paste during stenciling. Finally, component beacon openings or translucent areas are made in the electronics assembly at component locations. After component placement, the board is appropriately lit, and any uncovered openings indicate missing or grossly misaligned components.

Abstract: The operation of a stream buffer varies depending on whether a normal operation mode or a test mode is selected. In the normal operation mode, the stream buffer is read from only when the data requested by a CPU read has been determined to reside there, and the stream buffer location read from is the location determined to contain the requested data. This determination is made by comparing the address of the read request with addresses of the data stored in the stream buffer. Also, the stream buffer is written with memory data in response to a read that misses the stream buffer, and the location written to is one that has been allocated to receive the incoming memory data. Two different buffer allocation methods are shown, first-in-first-out (FIFO) and least-recently-used (LRU).

Abstract: A method and apparatus for controlling memory access operations of a pipelined processor using a "write queue" are described. The write queue temporarily stores addresses of writes not yet made in memory. Each write queue entry includes a write-read conflict bit. When an entry is first put into the write queue, the write-read conflict bit is cleared. When a subsequent memory read request occurs, the address of the read request is compared to the addresses stored in the write queue. If there is a match, the write-read conflict bit in the matching entry is set. If after this comparison no conflict bits are set, the read is allowed to proceed to memory before the queued writes. On the other hand, if any conflict bits are set, the read is prevented from proceeding. The conflict bits are cleared as the queued writes are performed in memory. Also, the write queue is able to accept additional entries while a read request is stalled.

Abstract: This invention relates to a method by which an electrical interconnect device is manufactured. In the preferred embodiment of the invention, the geometric dimensions of the device and its necessary electrical characteristics are determined by reference to the components which the device is going to interconnect. An electrically conductive skin thickness, which will achieve the necessary electrical requirements of the application, is also determined. That conductive skin is then selectively formed over an electrically non-conductive core, which is constructed in accordance with the geometric requirements and electrical operating properties of the application, but which is deliberately undersized by the thickness of the skin. Thus, when the skin is formed over the undersized core, the skin thickness causes the final device produced by the process to meet both the electrical and geometric requirements of the application.