Abstract: An apparatus and method for training of auditory and graphical discrimination in humans is provided. The method and apparatus provides a number of stimulus sets, each stimulus set having a target phoneme, and associated grapheme, and a number of distractor phonemes, and associated graphemes. Upon initiation of a trial, a target phoneme is presented to a subject. A stimulus stream is then prepared that consists of a random sequence of distractor phonemes. Located within the sequence of distractor phonemes is the target phoneme. The stimulus sequence is presented to the subject for identification of the target phoneme within the sequence. Speech processing is used to provide multiple levels of emphasis for enhancing a subject's ability to discriminate between similarly sounding phonemes. The processing is applied to the presentation of the target phoneme and the stimulus stream.

Abstract: An apparatus and method for loading a pointer into a selector register/general purpose register pair is provided. The apparatus and method utilizes a single micro instruction to load an offset directly into the general purpose register, during the write back stage of a pipeline, while storing the old value in the general purpose register into a temporary register, in an earlier stage in the pipeline. Thus, the general purpose register is overwritten with the offset before the selector load completes. If the selector load operation fails, the general purpose register may be restored from the temporary register.

Abstract: An apparatus and method for measuring parasitic differences between dissimilar conductive paths on a semiconductor is provided. The apparatus provides a ring oscillator which has two propagation paths. The first path is traversed on a logical transition from low to high, and the second path is traversed on a logical transition from high to low. The gate stages for the first path may be interconnected via a metal conductive layer, and the gate stages for the second path may be connected to a dissimilar metal, or polycide, for example. A single output signal is produced which has a period equal to twice the delay of the inverter stages, plus any delay associated with the parasitic difference in the two paths. The duty cycle of the periodic signal may then be used to determine the parasitic difference between the two materials used to interconnect the stages in the ring oscillator.

Abstract: To facilitate the reworking of a multi-tiered circuit board and a laminated multi chip module, a chip module apparatus having a substrate portion is provided. The chip module has first and second opposite sides with vias extending therethrough. Deposited on both sides of the module by conventional processes is a layer of copper. A first mask is applied to the copper layer to expose a copper, electrical circuit pattern. A second mask having holes therein that are offset from the vias is placed over the first mask by conventional processes. Formed on at least one of the chip module's side in the second mask's holes are a spaced series of an solder BGAs, which have melting point temperatures substantially greater than the phase transition temperature of the chip module's substrate portion. The BGA's are formed on the chip module by an electrochemical plating process.

Abstract: A portable computer system wherein the printer port can be used, at the user's option, not only for connection to a printer, but also for connection to an external floppy disk drive. If the BIOS determines that there is an external floppy drive attached, the BIOS disables the normal operation of the parallel port in order to allow the external floppy to operate.

Abstract: A disk drive array with a controller which provides: dynamic remapping for grown defects in the disk drives, multi-thread request processing with a variable number of forkings, defect tracking with both logical and physical lists, guarded writes of less than a full stripe optimized by selectably using the redundancy to limit the number of sectors involved, association of multiple operations with a single disk request in order to facilitate error handling, use of an access hiatus as indication of further opportunity to rebuild data in background, and scatter/scatter (bidirectional scatter/gather) operations.

Abstract: Disclosed are a system and method for loading diagnostic routines for execution in a computer system. The method comprises the steps of (1) executing a boot loading routine stored in non-volatile memory within the computer system, the boot loading routine providing an environment in lieu of an operating system of the computer system within which to execute diagnostic routines, the boot loading routine including a decompression routine, (2) decompressing a compressed diagnostic routine stored in the non-volatile memory into video random access memory (RAM) and (3) executing the decompressed diagnostic routine under control of the boot loading routine. The present invention, in its preferred embodiment, allows relatively large diagnostic routines to be stored in electrically erasable programmable read only memory ("EEPROM") and decompressed, as required, into video RAM for execution, without requiring the computer's operating system to function.

Abstract: Method and apparatus for power management of a RAM subsystem of a computer. Blocks of data stored at various addresses throughout the RAM subsystem are packed into unallocated memory space at the lowest possible physical location within the RAM subsystem and then are compressed. The packed and compressed data is then copied into the minimum number of RAM devices comprising the subsystem needed to store such data. The remaining RAM devices are either deenergized, if they comprise static RAM, or not refreshed, if they comprise dynamic RAM, thereby reducing the power consumption of the subsystem. Upon a command to return from the reduced power consumption mode, the above steps are executed in the reverse order and the blocks of data are copied to their original memory address locations in said RAM subsystem, using a table that is compiled during the packing step.

Abstract: A personal computer system utilizes a simplified motherboard having connectors on the motherboard that are electrically connected to data, address, control, power and ground signals necessary for expansion and upgrade of the computer system and a riser card or cards having the desired interface connectors and logic circuits thereon. The present invention provides for operatively and removably coupling a plurality of I/O expansion cards, host local bus interfaces and future system upgrades for the computer system without burdening the base cost thereof. The computer system may be expanded or upgraded at any time during manufacture or in the field. A simple and low cost common motherboard is utilized in the manufacture of the computer systems, resulting in lower manufacturing costs. A base computer system may be easily upgraded when more features are desired.

Abstract: A modem assembly for a computer is disclosed that includes a cavity that receives a PCMCIA Modem Card which is displaced a distance x within the interior of the computer housing. The PCMCIA Modem Card includes a standardized PCMCIA Modem input/output connector. The modem assembly includes a connector block that comprises a body potion and an end cap. The body potion of the connector block includes one or more telephone sockets that are mounted flush to the exterior surface of the computer enclosure. The end cap protrudes downwardly and outwardly from the body potion, with a thickness x and a width and height approximately equal to the cross-sectional height and width of the PCMCIA Modem Card, to mount flat with the computer enclosure and to seal the PCMCIA Modem Card within the computer enclosure. The end cap includes an electrical socket that mates physically and electrically with the standardized PCMCIA input/output connector.

Abstract: A memory write disable circuit which disables write operations to main memory during cache diagnostics and thus provides a generic means for testing cache memory systems. Disabling write operations to main memory allows the diagnostics to easily distinguish between cache hits and cache misses during diagnostics. The disable circuit operates by disabling the output enable for the main memory write signal. This disables writes to main memory in a manner external to the memory controller and thus allows tags to be loaded from a cacheable space in main memory. This enables the testing of cache memory systems in computer systems using integrated cache and memory controllers which prevent read hits to memory addresses whose cacheability has been disabled. This also provides a testability function that is hardware independent and thus can be used regardless of the configuration or processor used in the computer system.

Abstract: A computer chassis having a port adapted to be configured to receive electrical connectors of differing dimensions therethrough and a method of manufacturing such configurable ports.

Abstract: A generally plate-shaped adapter device has an inner edge portion with spaced bosses thereon that may be snapped into tooling holes in a printed circuit board which is smaller than the circuit board originally designed to be secured to mounting portions formed on a computer chassis wall. The in-place adapter device forms an outward edgewise extension of the smaller circuit board and has an outer edge portion positioned and configured to cooperate with the chassis board mounting structure in a manner permitting the reduced size printed circuit board to be operatively mounted on the chassis wall without modification of its board mounting structure.

Abstract: A keyboard structure is recessed within an open-topped base housing portion of a compact portable computer such as a notebook or laptop computer. Front comer portions of the keyboard structure are secured to the base housing in a manner permitting the keyboard structure to be pivoted relative to the base housing between a storage/transport orientation in which the top side of the keyboard structure is generally parallel to the bottom side of the base housing, a tilted use orientation in which the top side of the keyboard structure slopes forwardly and downwardly toward the user and an access position which allows easy access to the interior portion of the computer for making modifications to a mother board that has been positioned in the upper interior portion of the base housing. A resilient latch assembly has cooperable detent structures that are disposed on the keyboard structure and the base housing.

Abstract: Disclosed are an integrated mouse tray and mouse for a portable computer and method of operation therefor. The computer, including the mouse tray of the present invention, includes: (1) a chassis having a footprint and containing components of the computer, the components including an interface circuit for communicating with a mouse, (2) a mouse electrically coupled to the interface circuit, the mouse free to move about a substantial plane to produce signals for transmission to the interface circuit and (3) a mouse tray member movably mounted to the chassis and capable of assuming a deployed position whereby the mouse tray extends substantially out of the chassis footprint, a substantially planar surface of the mouse tray providing an area on which the mouse is free to move to produce the signals, the mouse tray member further capable of assuming a stowed position whereby the mouse tray is retracted substantially to within the chassis footprint.

Abstract: A printed circuit board is provided having a beveled edge for ease of insertion into a receptor. The beveled edge is extended onto the solder mask to present a contiguous beveled surface. Moreover, the PCB includes bonding pads which can be surface mounted with pins extending from the receptor. Each bonding pad includes a forward portion and a rearward portion. The forward portion is covered with the solder mask layer to present a smooth surface channeled inward in a V-shaped configuration. The forward portion channels or directs the pin along a central axis near the apex of the V-shaped forward portion onto the upper surface of the bonding pad rearward portion. Accordingly, the pin is channeled to an area absent solder paste along the central axis such that during subsequent reflow operation the solder paste is reliably extended over and around the centrally placed pin.

Abstract: A small computer architecture in which the CPU can receive multiple kinds of interrupt signals, including one kind which is assigned to indicate the occurrence of a keystroke input and another kind which is assigned to indicate the occurrence of a pointing device input. However, the computer does not include any pointing device as such. Instead, the keyboard microprocessor (i.e. a microprocessor other than the CPU) monitors user keystrokes to the computer's keyboard, and: in response to simple keystrokes, or keystroke combinations which include one of the basic chording keys, the keyboard microprocessor sends a keystroke interrupt to the CPU; and in response to keystroke combinations which include an additional chording key, the keyboard microprocessor sends a pointing-device interrupt to the CPU, and provides a data output corresponding to an emulated pointing-device movement.

Abstract: A computer system where memory access is accelerated by automatically incrementing the address at the memory chip inputs, as soon as the minimum hold time has occurred. If the next address actually requested by the CPU does not match this predicted address, then the actual address is driven onto the chip inputs as usual, so essentially no time is lost. However, if the automatically incremented address does match the next actually requested address, then a significant fraction of the chip's required access time has been saved.

Abstract: An improved read ahead strategy that improves the performance of a disk array subsystem. The disk controller keeps track of the last n reads to the array. If a new read request is received that is adjacent to any of the last n reads, the controller performs a look ahead read because a sequential read may be in progress. The parameter n is preferably set comparable to or greater than the number of maximum independent activites being performed by the computer system. Therefore, in a multithread system, the controller performs a readahead if any one thread is doing a sequential read.

Abstract: A method and apparatus which provides bi-directional communication between a video monitor and a computer system unit. This enables the video monitor to inform the system unit of its capabilities without direct user involvement and also enables the system unit to directly control or adjust all the functions of the video monitor. In the preferred embodiment, bi-directional communication between the video monitor and the system unit is provided utilizing a mouse port in the keyboard controller. Multiplexors are coupled between the mouse port and each of the mouse and video monitor to select between data paths and selectively allow communication between the system unit and the video monitor. Monitor control software is included in the system unit which can be used to control or adjust the output of the video monitor.