Abstract: The data processing system of the invention comprises a processor, a memory access controller and a memory hierarchy. The memory access controller is placed between the processor and the memory hierarchy and controls access thereto. The memory access controller comprises a cache controller and a translation unit which are connected in parallel to an address bus connected to the processor and by which virtual addresses are transported. The memory access controller supports segments which are unit of sharing the memory, each segment is split up into pages. The memory access controller also supports regions which contain at least one segment. The memory access controller further supports sectors, divided into blocks which are other units of sharing the memory. And the memory access controller is also provided for enabling access with I/O units.

Abstract: A cryptographic validation for an external station of a communication system provided with a central data processing device, a number of access stations which are coupled thereto and a number of external stations which can be selectively coupled to the access stations. To validate an external station, the access station transmits a message encoded by a first encoding key. The external station decodes the message received and re-encodes the message using a second encoding key, transmitting the re-encoded message back to the access station. The access station then decodes this message using a second key decoder. This decoded data is compared with the data originally encoded by the access station. If the data is identical, the external station is validated.

Abstract: The data processing system according to the invention has a microprocessor and an external erasable and programmable memory. A logic connection system is arranged between control pins of the microprocessor and a controlled pin of the external memory. These control pins of the microprocessor are the program control pin, a port control pin, the controlled pin of the memory and the memory selection pin. This ligic connection system permits using only one memory both for reading and writing of instructions and/or data instead of the two memories generally used.

Abstract: A pressure sensitive fault interrupter for a dry metalized AC motor run capacitor having a dome-shaped diaphragm secured to one electrode at the base of a capacitor roll such that a rise in pressure within said roll will cause the dome of the diaphragm to be depressed, thereby breaking the electrical contact of one electrode, thus isolating the capacitor from its power supply.

Abstract: A fail-safe lead configuration for surface mountable chip-like polar electrical components wherein the lead of a first polarity is singulated and the lead of the second polarity is bifurcated, having the branches spaced a part such that a rotation of the device in its intended mounting location, thus reversing its polarity, or a displacement from its intended, position will result in an open circuit rather than a short circuit or other circuit failure.

Abstract: A system for packaging leadless electronic and electrical components for automatic component placement machines including a low-cost, disposable, flexible engineered laminated carrier tape on which leadless components are held, a reel for winding said component tape, the reel being fabricated with a core of solid fiber chipboard and side discs sheets of coated kraft paper such that the carrier tape may be sealed within the coated paper side sheets of the reel and peeled from side sheets while unwinding.

Abstract: A very large scale integrated circuit comprises a number of function blocks which are synchronized by relevant clock signals. Each function block forms an isochronous region so that the delay times of the signals within the relevant function block can be negligibly small with respect to the gate delay times. Each function block is paired with at least one other function block in that the pair is connected by an information connection and by at least two synchronization handshake lines for transporting synchronization signals dispatched by each function block of the pair to the other function block of the pair so that an asynchronous information transport is obtained. One or more of the function blocks comprises an information connection to the environment. As a result of this set-up, the circuit can also be tested and designed per function block.

Abstract: A method of and a device for placing chip-type components on a substrate, in which a number of components are simultaneously picked up in presentation positions by means of a pick-up device which has a number of pick-up elements, after which the pick-up device is moved to a position over the substrate and each of the pick-up elements in succession is moved to a position over the desired position on the substrate by movement of the pick-up device and/or the substrate with respect to one another, after which the relevant component is deposited and released in the relevant position by the pick-up element.

Abstract: A decoding system for code words which are protected against the occurrence of a plurality of symbol errors within a code word by means of a Reed-Solomon code. After the formation of the syndrome symbols, the key equation is solved, assuming the least possible number of symbol errors. When a plausible number L is found using 2L syndrome symbols, an additional number of syndrome symbols is considered for determining the discrepancy quantity. The locator equation is directly solved when it is of a low order. For a higher order, a Chien search cycle is performed and any symbol error found is removed by division until the order becomes low enough for direct solution. The decoding system is suitable for implementation by means of a microcomputer and for use in a reading device for optically readable record carriers.

Abstract: A circuit arrangement having a plurality of circuit units (1-l to 1-n) each circuit unit (1-l to 1-n) having an input AI and and output AO. Each circuit unit (1-l to 1-n) includes an address generator which is incremented by a clock signal applied via terminal. Incrementation of the clock generator is inhibited when a logical `1` is applied to the input AI of a circuit unit. In order to generate addresses for all the circuit units they are connected in a daisy chain with the AO output of each circuit unit being connected to the AI input of the next circuit in the chain. The circuit units (1-l to 1-n) are arranged so that when a logical `1` is applied to its AI input a logical `1` appears at its AO output one clock period later. A monitoring unit may be provided to detect when all addresses have been set up by monitoring the state of the AO output of the last circuit unit (1-n) in the chain.

Abstract: A bi-plane phased array transducer for real time medical imaging having a composite piezoelectric disk with an array of transducer-element electrodes disposed on each major surface of said disk, the array on one side being at an angle to the array on the other side and electrical connections to ground each array alternately so that real time sector imaging in two planes is obtained.

Abstract: A method and machine for testing data processing systems wherein the test result is an acceptance or another condition for the central processing unit of the data processing system. For each data processing system having an intended configuration, the method embodies one or more test programs, each program requiring a predetermined configuration of peripheral devices, the execution of a specific test program being started only after the verification of the presence of the required peripheral. In the absence of an intended peripheral, the test machine has means for simulating the presence of said peripheral device. The determination of the peripherals in a configuration and the selection of a test program from a library of such programs may be automatic or may be chosen by operator input.

Abstract: A multisection AC capacitor having a pressure sensitive fault interrupter, said capacitor being a dry metallized AC motor start and motor run capacitor, said fault interrupter having a dome shaped diaphragm secured to one electrode at the base of one capacitor section within said unit and one or more core connectors spatially separating and securing said capacitor sections within a sleeve such that the multisection stacked capacitor may be potted within a case and gases resulting from a build up of pressure within said capacitor will be directed to its core and downward therefrom to exert pressure, causing the dome of the diaphragm to be depressed, thereby breaking the electrical contact of one electrode, thus isolating the capacitor from its power supply.

Abstract: A multisection AC capacitor wherein each capacitor section has a pressure sensitive fault interrupter having a dome-shaped diaphragm mechanically and electrically secured to a contact bridge at the base of the capacitor roll, all capacitor sections within said case being electrically connected in parallel, such that a rising pressure within one section will cause the dome of the diaphragm of the faulty capacitor to be depressed, thereby breaking the electrical contact of one electrode, thus isolating the faulty capacitor from the power supply, while permitting the remaining capacitors in the multisection unit to function normally.

Abstract: Computer aided design method and apparatus which automatically generate pin-to-pin interconnection lists between respective discrete electrical component circuits. Input devices provide for entering a list of components used, a description of those components and the circuit interconnection description. The memory store contains a library of standard component descriptions. A processing unit process the entered circuit description and selected component descriptions from storage to produce an interconnection list in the form of an individual component pin to individual component pin connection.

Abstract: A pressure sensitive fault interrupter for an oil impregnated metallized AC motor start and motor run capacitor having a dome-shaped diaphragm secured to one contact electrode bridge at the base of the capacitor roll such that a rise in pressure within said roll will cause the dome of said diaphragm to be depressed, thereby breaking electrical contact of one electrode, thus isolating the capacitor from its power supply.

Abstract: A multiprocessor computer system having n parallel-operating computer modules which each include a processor module, a memory module and a data word reconstruction module, wherein each module of said system processes the same piece of data simultaneously and in parallel. The data words are applied to a reducing encoder so that code symbols stored in the relevant computer modules form a code word. The relevant error-correction code has a simultaneous correction capability in at least two code symbols. Each data word reconstruction module receives the entire code word in order to reconstruct the data word therefrom. Each computer module also has an input/output memory module. This module receives a coded data word which is decoded when it is presented again. Decoding is performed so that each bit in the input/output memory is mapped on at the most one bit of the associated memory module.

Abstract: A flip-flop with a built-in enable function realized by the addition of two transistors between the trigger circuit and the output nodes of the flip-flop. This embodiment of the enable function causes no increase in power dissipation and may be used in any type of flip-flop.

Abstract: A multiprocessor system for forming a color picture from object elements defined in a hierarchic data structure. The object elements are Bezier polygons each of the sides of which forms a Bezier curve. There is provided an array of parallel connected point processors which perform three functions. First of all, from the highest level of the data structure they determine the relevance of each object element to a point in question until either irrelevance is detected or one or more elementary object elements remain. Furthermore, for each point and each relevant elementary object element a binary inside/outside determination is made. Finally, the color is implemented by a priority determination of the elementary object elements determined to be "inside". The inside/outside decision is made in that during successive steps the relevant polygon sides are divided and in that the contribution to the inside/outside determination by the parallelogram diagonalized by the current side portion is decided.

Abstract: A circuit arrangement for supplying interrupt requests signals from a peripheral unit to a central processing unit of a computer system over a common control line, without a priority scheme. A blocking circuit is provided such that the first interrupt signal on the common control line blocks any further interrupt signals on that line until the interrupt has been processed. Since no further interrupts are possible, the interrupt acknowledged signal from the central processing unit need not contain the address of the external unit having requested the interrupt nor need there be provided a circuit to process the interrupt acknowledge signal in the peripheral unit. An interrupt signal present on the common interrupt line blocks generation of subsequent interrupt signals from reaching the common interrupt line by a combination of the two interrupting switches together with a delay after the first switch.