Abstract: A semiconductor device (50) includes a semiconductor die (20) having a first surface (14) for forming electronic circuitry. A coating layer (16) formed on a second surface (15) of the semiconductor die has a color that contrasts with the color of the semiconductor die. The coating layer is patterned to expose a portion of the second surface to reveal information pertaining to the semiconductor device. The coating layer is patterned by directing a radiation beam (30) such as a laser to selectively remove material from the coating layer.

Abstract: A semiconductor device (10) includes a semiconductor die (20) and an inductor (30, 50) formed with a bonding wire (80) attached to a top surface (21) of the semiconductor die. The bonding wire is extended laterally a distance (L30, L150) greater than its height (H30, H50) to define an insulating core (31, 57). In one embodiment, the inductor is extended beyond an edge (35, 39) of the semiconductor die to reduce loading.

Abstract: An inrush current limiter circuit (20) includes a detection circuit (30) that produces a control signal (VDRIVE) from a sense current (ISENSE). A power transistor responds to the control signal and has a source (51) coupled to an input node (12) to receive a supply voltage (ground) and a drain (53) for routing a load current (ILOAD) to an output node (45) as a protection signal (VSW). A sense transistor responds to the control signal and has a source scaled to the source of the power transistor and coupled to the input node to route a portion of the load current to the output node as the sense current.

Abstract: A transistor (10) is formed in a semiconductor substrate (12) whose top surface (48) is formed with a pedestal structure (24). A conductive material (40) is disposed along a side surface (28) of the pedestal structure to self-align an edge of a first conduction electrode (45) of the transistor. A dielectric spacer (55) is formed along a side surface (49) of the conductive material to self-align a contact area (56) of the first conduction electrode.

Abstract: A filter circuit (10) is formed on a semiconductor substrate (11) formed with a trench (40) that is lined with a dielectric layer (38). A conductive material (37) is disposed in the trench and coupled to a node (62) to provide a capacitance that modifies a frequency response of an input signal (VIN) to produce a filtered signal (VOUT). An electrostatic discharge device includes an inductor (74) coupled to back to back diodes (17, 18) formed in the substrate to avalanche when a voltage on the node reaches a predetermined magnitude.

Abstract: An integrated detector circuit (20) includes first and second gain stages (GS1, GS2). The first gain stage has an input (82) that monitors a high frequency signal (VRFDET) for routing a first detection current (IS1) to a node (60). The second gain stage includes a first current source (PF1) that supplies a bias current (IMAX1) indicative of a predefined amplitude of the high frequency signal. An input of the second gain stage monitors the high frequency signal to route a portion of the bias current to the node as a second detection current (IS2), which is limited to the bias current when the high frequency signal is greater than the predefined amplitude to compensate for a nonlinearity in a transconductance of the second gain stage.

Abstract: An integrated circuit package (60) has a substrate (12) with a first surface (51) for mounting a semiconductor die (20) and a second surface (52) defining a via (70). A lead (26) is formed by plating a conductive material to project outwardly from the second surface. The conductive material extends from the lead through the first via for coupling to the semiconductor die.

Abstract: A transistor (10) is formed on a semiconductor substrate (12) with a first surface (19) for forming a channel (40). A gate dielectric (22) has a first thickness overlying a first portion of the channel, and a dielectric film (20) overlies a second portion of the channel and has a second thickness greater than the first thickness. The second thickness reduces the drain to gate capacitance of the transistor, thereby improving its switching speed and frequency response.

Abstract: An inrush current limiter circuit (20) includes a mirrored transistor (50) responsive to a control signal (VDRIVE) developed from a sense current (ISENSE), and has a first source (51) coupled to a supply voltage, a common drain (53) that routes a load current (ILOAD) to an output node (45), and a second source that samples the load current to produce the sense current. A fault protection circuit (64) disables the mirrored transistor in response to a first fault condition (TEMP, UVLO) and is coupled to a first lead (43) for externally adjusting a fault threshold. A fault communication circuit (250) is coupled to the first lead to receive a fault signal representative of an external fault condition to disable the mirrored transistor.

Abstract: A method of making a semiconductor device 10 by forming a first dielectric layer 140 on a substrate, etching through the first dielectric layer to form a trench 150 having a channel region 135 on a sidewall 160 of the trench, and laterally removing a portion of the first dielectric layer adjacent to the sidewall of the trench above the channel region for defining a source region 280 of the semiconductor device.

Abstract: A semiconductor device (20) has a first leadframe (200) with a first semiconductor die (70) electrically coupled to one of its leads. A second semiconductor die (130) is mounted to a second leadframe (300) that has a first lead (35, 150) electrically coupled to the second semiconductor die and a second lead (30, 35) mounted to the lead of the first leadframe.

Abstract: A semiconductor structure (1), comprising a isolation region (5) formed on a semiconductor material (10). A pillar (15) is formed in the semiconductor material under the isolation region, where the pillar is capped with a first dielectric material (20) to form a void (16).

Abstract: An integrated circuit (100) includes high performance complementary bipolar NPN and PNP vertical transistors (10, 20). The NPN transistor is formed on a semiconductor substrate whose surface (24) is doped to form a PNP base region (28, 70). A film (32, 34, 30) is formed on the surface with an opening (42) over an edge of the base region. A first conductive spacer (48) is formed along a first sidewall (78) of the opening to define a PNP emitter region (67) within the base region. A second conductive spacer (47) is formed along a second sidewall (76) of the opening to define a PNP collector region (66).

Abstract: A method of making a semiconductor device (10) includes depositing a first conductive layer (50) on a first surface (41) to control a channel (70) of the semiconductor device at a second surface (40) perpendicular to the first surface. The method further includes etching a first dielectric film (32) to form a gap (53) between the first surface and a control electrode (68) of the semiconductor device, and depositing a conductive material (56) in the gap to electrically connect the first conductive layer to the control electrode.

Abstract: A smart card reader (8) includes a detection circuit (26) that has a plurality of inputs (30, 38, 42) for monitoring a plurality of operating conditions of the smart card reader. A plurality of outputs (53-56) provide a plurality of sense signals (VCCOK, VCCOC, VBATOK, CRDINS). A multiplexer (60) has a plurality of sense inputs coupled to the plurality of outputs of the detection circuit. A selection input (67, 68) receives a selection signal (ADDR) for routing one of the plurality of sense signals to an output (32) as a status signal (STATUS).

Abstract: A semiconductor package (101) has a die (1), a leadframe (4), a bond pad (6), an encapsulation (3) and a wire bond ball (2). The wire bond ball is formed on the bond pad by bonding one end of a bond wire (7), and remainder of the bond wire is removed. Locations (23) for attaching the wire bond ball are recorded with reference to fiducials (5) on the lead frame. The encapsulation covers the die, deposits and die attach flag (24) of the lead frame. The wire bond ball is exposed where the encapsulation is removed. The locations for making openings (17) for exposing the wire bond ball is determined by recorded coordinates when the wire bond ball is formed. Exposed wire bond ball is plated, forming a lead to electrically connect to the die.

Abstract: A semiconductor switching device (10) is formed on a semiconductor substrate (12) having a trench (44) formed on one of its surfaces (42). A control electrode (32) activates a wall of the trench to form a conduction channel (36). A first conduction electrode (40) is disposed on the semiconductor substrate to have a first doped region (34) for receiving a current and a second doped region (24) for routing the current to the conduction channel.

Abstract: An integrated circuit (10) includes a thermal shutdown circuit that incorporates hysteresis for shutting down a functional circuit (13) when its temperature exceeds a predefined value. First and second current sources (18, 17) respectively produce first and second reference currents (IREF1, IREF2) representative of first and second die temperatures of the integrated circuit. A current mirror (14) has an input (19) for summing the first and second reference currents and an output (15) for providing a mirror current (IMIRROR). A detection circuit (12) has an output coupled to the output of the current mirror for sinking the mirror current to produce a detection signal (VDET) as a function of the first and second die temperatures.

Abstract: An amplifier (170) includes first and second depletion mode transistors (161, 162) operating in response to first and second complementary signals (VAMP+, VAMP−), respectively, which route a first current (ISTACK1) from a first supply terminal (171) to an output (169) of the amplifier. Third and fourth depletion mode transistors (163, 164) receive the first and second complementary signals to route a second current (ISTACK2) from a second supply terminal (Ground) to the output. The first and second currents are summed to produce an output signal (VAMP2).

Abstract: An integrated circuit (100) includes a semiconductor die (102, 103) and a semiconductor package (101) that has a leadframe (20, 40, 60, 80) for mounting the semiconductor die. The leadframe includes a first laminate (20) whose bottom surface (7) is patterned with leads (106, 107, 131, 132) of the integrated circuit. A second laminate (40) has a bottom surface (3) attached to a top surface (5) of the first laminate to electrically coupling the leads to the semiconductor die.