Abstract: A power amplifier driver (16) provides control voltage inputs to power amplifier (14) at terminal (OUT). An output power control loop is implemented through directional coupler (20) and power amplifier driver (16). Power amplifier driver (16) implements a loop integration function utilizing transconductance amplifiers (60, 62) to convert a detection signal (DET) and a reference signal (REF2) to current for summing at node 58. Transconductance amplifiers (70,72) convert the error voltage generated at node (34) and bias voltage (Vmin) to current for summing at node (36) for subsequent conversion back to voltage by resistor (74). The error voltage at node (36) is buffered (26) to provide adequate current drive at terminal (OUT).

Abstract: A method of making a semiconductor device (100) by attaching a top surface of a first laminate (630) to a bottom surface of a second laminate (650) to form a leadframe (620) and mounting a semiconductor die (102) to the leadframe to form the semiconductor device. The first semiconductor die is encapsulated with a molding compound (108) and material is removed from the first laminate to form a mold lock (120) with the molding compound.

Abstract: A semiconductor device (20) has a first leadframe (200) with a first semiconductor die (70) electrically coupled to one of its leads. A second semiconductor die (130) is mounted to a second leadframe (300) that has a first lead (35, 150) electrically coupled to the second semiconductor die and a second lead (30, 35) mounted to the lead of the first leadframe.

Abstract: A semiconductor device (10) includes an electrical component (70) formed on a dielectric region (22) of a semiconductor substrate (12). The dielectric region is formed with a first plurality of voids (58) extending into the substrate to a first depth (D31) and a second plurality of voids (56) extending into the semiconductor substrate to a second depth (D30) greater than the first depth.

Abstract: A power converter circuit (23) and a method for controlling current in a transformer (16). The power converter circuit (23) includes a controller circuit (60), a duty cycle detector circuit (61), a soft start circuit (62), and a switch (63). The switch (63) controls the current in the transformer (16). The controller circuit (60) cooperates with the soft start circuit (62) to alter the duty cycle of the switch (63). During initial start-up, the switch (63) operates at a minimum duty cycle and increases towards a maximum duty cycle to prevent transformer (16) saturation and potential failure of the switch (63). In addition, the duty cycle detector circuit (61) alters the frequency at which the switch (63) turns on and off to reduce the power consumption of the power converter circuit (23).

Abstract: A method of making a semiconductor device (10) having a low permittivity region (24) includes forming a first layer (30/42) over a surface of a trench (20), and etching through an opening (70) in the first layer that is smaller than a width (W2) of the trench to remove a first material (38) from the trench. A second material (44) is deposited to plug the opening to seal an air pocket (40) in the trench. The low permittivity region features air pockets with a high volume because the small size of the opening allows the second material to plug the trench without accumulating significantly in the trench.

Abstract: A method of making a semiconductor device (10) includes filling a plurality of trenches (30, 32-34) in a substrate (11) with a first fill material (40, 42-44) and lined with a first liner material (36-39) to form an isolation structure (50) in a first trench (30). The first fill material and the first liner material are removed from a second trench (33) which is then lined with a second liner material (46) and filled with a second fill material (69) to produce a capacitance to the substrate. The first fill material and the first liner material are removed from a third trench (34), which is filled with the second fill material to form an electrical contact to the substrate. The first fill material is removed from a fourth trench (34) and dielectric material (78) is deposited on the substrate to produce a void (83) in the fourth trench.

Abstract: A semiconductor device (20) is formed on a substrate (21) that has first and second well regions (25, 26) formed at a surface (18) of the substrate. A control electrode (34) extends over the surface to activate a first channel (42) with a control signal (V14) for routing a current (IN) from a first node (13) of the semiconductor device to an edge (43) of the first well region. The control signal further activates a second channel (46) for routing the current from an edge (45) of the second well region to a second node (15) of the semiconductor device.

Abstract: Voltage regulator (10) provides current sense comparator (18) to detect the normal and standby modes of operation for voltage regulator (10). During a normal mode of operation, current sense comparator (18) de-asserts signal (MODE), causing voltage regulator (10) to regulate the output voltage to a predetermined level. Once the current (Iin) has diminished below a predetermined value, current sense comparator (18) asserts signal (MODE) to indicate a standby mode. During the standby mode, regulator (10) regulates the output voltage (Vout) between first and second reference levels, requiring a quiescent current level much less than the quiescent current level required during normal mode, due to the deactivation of current sense comparator (18) and error amplifier (28) during standby mode. An alternate method of quiescent current reduction uses switched voltage reference (86).

Abstract: A regulator circuit (10) includes an amplifier (61) having an input for sensing an output signal (VS, ILOAD) of the regulator circuit and an output (13) for producing a transient signal (ITR1, ITR2) in response to a change in the output signal. A feedback path (62, 67, 70) is coupled between the output and the input of the amplifier to set a gain of the amplifier to a first value when the output signal is constant and to a second value when the output signal changes. The feedback path includes a level shift circuit (62, 65) having an input (81) that receives the output signal and an output (83) that produces a level shifted signal for biasing the output of the amplifier to a predetermined level.

Abstract: An integrated switching mode power supply (10) has a follower device (59) providing a supply voltage (VBOOT) to a node (70) of the power supply. A driver circuit operates in response to an input signal (VCONTROL) and has an output (40) for providing a drive signal (VDRIVE) that bootstraps the node to a potential greater than the supply voltage.

Abstract: A power supply (10) has a first transistor (20) coupled for switching a coil current (Il9) in response to a first control signal (VC1). A second transistor (30) has a body diode (32) for discharging the coil current to produce a power factor corrected signal (VPFC). A conduction channel (31) of the second transistor is responsive to a second control signal (VC3) for developing a second coil current (I61) from the power factor corrected signal to adjust an output signal of the power supply, where the second control signal commences a time interval (TD2) after the first control signal terminates.

Abstract: An integrated power supply (106) is formed on a semiconductor substrate (200). A first switch (150) is formed in a well region (155) of the semiconductor substrate to have a conduction path (211) for coupling a supply voltage (VBAT) to a node (116). A second switch (152) operates in response to a first control signal (COMP) for coupling the node to the well region when a potential of the node is greater than the supply voltage.

Abstract: A semiconductor device (10) has a substrate (20) with a surface (26) for defining a trench (34). A control electrode (45) is disposed at the surface to activate a conduction path (50) along a sidewall (36) of the trench with a control signal (VGATE). A dielectric layer (32, 35) is formed between the sidewall and the control electrode to have a first width (WGS) adjacent to the surface and a second width (WGC) smaller than the first width adjacent to the conduction path.