Abstract: A digital phase quantized frequency modulation (FM) detector (300) is for a communication receiver (100). A digital phase FM quantizer receives (310) I and Q signals (221, 222) derived from a received FM signal (119) and generates a coded position word (381) of width M bits at the beginning of each period of a sample clock (190) that identifies a sector location of a phasor representing the I and Q signals. A two's complement converter (400) converts the coded position word into a two's complement position word of width M bits. A differentiator (420) of width M bits generates a two's complement difference word which represents a change of a phase angle of the phasor in magnitude and direction during each period of the sample clock. A digital post detection filter filters consecutive two's complement difference words and generates therefrom a reconstructed digital demodulated signal (461).

Abstract: An interactive method for composing an alphanumeric message by a caller using a telephone keypad includes storing (215) a lexical database (135) from which unigram probabilities, forward conditional probabilities, and backward conditional probabilities for a plurality of words can be recovered; storing a received sequence of key codes (405) representing a sequence in which keys on a telephone style keypad are keyed; generating a word trellis including candidate words (415) derived from the sequence and the lexical database; determining a most likely phrase (420) from the candidate words, the unigram probabilities, forward conditional probabilities, and backward conditional probabilities; generating a most likely message (425) from the most likely phrase and presenting the most likely message to the caller; and confirming that the most likely message is the alphanumeric message (430).

Abstract: A method is used in a selective call receiver (SCR) (100) for displaying information messages received by the SCR on a multiline display (124) of the SCR. According to the method, a plurality of information messages is received (405), wherein each of the plurality of information messages has an identifiable source. An operator selection (415) of a paramount source is determined. An information message associated with the paramount source is automatically displayed (430) on a line of the multiline display in a horizontal scrolling manner when the information message having the paramount source is determined to have a value different than a previously displayed value of an information message from the paramount source. Information messages that are not associated with any paramount source are displayed in a full screen manner (440) when such information messages are displayed in response to manipulation of controls.

Abstract: An electrical circuit includes a substrate having at least two alignment pads on the substrate that are accurately aligned with a first set of electrical interconnect pads, and also includes a corresponding number of alignment posts that are cylindrical and have flat bases that are geometrically similar to and smaller than a corresponding shape of each of the at least two alignment pads by a predetermined solder fillet radius. Each of the at least two alignment posts is reflow soldered to one of the at least two alignment pads. An electrical part can be accurately aligned to the substrate using the alignment posts, during attachment of the electrical part.

Abstract: A subscriber's PMU (Personal Messaging Unit) (14) determines when the number of incoming messages is likely to be excessive by counting the incoming messages and comparing their number and rate of receipt to stored thresholds. The subscriber is alerted when an excess is detected, and he is given options such as: routing future messages to himself via alternate and less expensive communication links (34,38), or terminating messages sent to one of his PMU's addresses that has been receiving messages at a high rate. Similar control can be effected at the PMU's base station (12).

Abstract: A computing device (100) including a wireless packet data communications modem (101) used in conjunction with a computer (103) to provide untethered access to data bases and other computer users. A method is provided for controlling data transmission and reception using the wireless packet data communications modem (101) in tandem with the computer (103). Two-way communications is achieved using a small, low-cost, light-weight wireless packet data communications modem contained in a housing, integral to a computing device, or a removable housing conforming to a PCMCIA industry standard.

Abstract: A direct conversion receiver (200) is capable of recovering a filtered baseband signal (295) from a radio signal (201) modulated with a baseband signal (202). The direct conversion receiver (200) comprises a radio frequency mixer (205) for converting the radio signal (201) to the baseband signal (202), a lowpass amplifier (210) DC coupled to the radio frequency mixer (205), that amplifies the baseband signal (202) and substantially attenuates components of the baseband signal above a high corner frequency, and a DC offset compensation section (225) DC coupled to the lowpass amplifier (210), that provides a DC offset compensation and a controlled highpass filtering of the baseband signal. A low corner frequency of the DC offset compensation section is smoothly varied from a predetermined maximum value to a predetermined minimum value during a low frequency, low energy portion of the signaling protocol.

Abstract: A Galois Field arithmetic logic unit (GF ALU) circuit (200) that generates a GF product of size M includes a first and a second input field element register (205, 210), a result field element register (215), a plurality, I, of subfield sets of logic gates (255, 260, 265), a plurality, S, of extension sets of logic gates (270, 275), and 3M switches (135). M is equal to S multiplied by I. A Galois Field of size M, S, and I each has an optimal normal basis. The first and second input field element registers (205, 210) are alternately coupled to the result field element register (215) by the I subfield sets of logic gates (255, 260, 265) in a first configuration and by the S extension sets of logic gates (270, 275) in a second configuration. The 3M switches (135) alternate the first and second configurations.

Abstract: A phase-frequency detector (110) includes an output stage (300) and a control stage (200). The output stage includes a pump up switched current source (350), a pump down switched current sink (360), and a constant current source (325) that are coupled to a charge pump output node (111). The control stage generates, in response to a divided variable frequency signal (FV) (136) and a reference frequency signal (FR) (106), a pump up control signal (246) and a pump down control signal (216).

Abstract: A low power switched diversity antenna system (200) includes two varactor tuned antennas (205, 207), each including an antenna element (505) and a varactor (515). The varactor tuned antennas intercept components of electromagnetic radiation that are substantially orthogonally polarized. One of the varactor tuned antennas is tuned to a desired frequency and the other is detuned, achieving a relative gain of the tuned varactor tuned antenna to the detuned varactor tuned antenna of at least 3 dB at the desired frequency.

Abstract: A sigma delta analog-to-digital converter (100) comprising a second or third order integrator block (105) featuring a feed-forward connection path between the input of the integrator block and an input of at least one of the plurality of integrators (130 or 150). A comparator (180) coupled to the output of the integrator block (105) generates as output a digital value representing a difference between the integrator output signal with respect to a threshold, or in a differential mode implementation, between component signals of a differential signal output by the integrator block (105). A digital sampling element (190) coupled to the output of the comparator (180) samples the output of the comparator (180) in response to a sampling clock signal at a predetermined sampling frequency to generate as output digital signal comprising samples of the digital values output by the comparator (180).

Abstract: A text compression technique used in a transmitter subsystem (126, 148) and a receiver subsystem (132, 158) for compressively encoding and decoding a text portion of a message by using tokens having at least two data symbol lengths. During encoding, a quantity of fill symbols are added to a sequence of secondary tokens, wherein the quantity of fill symbols is determined such that a total quantity of the data symbols in the sequence is equal to an integral multiple of the quantity of the data symbols having a first data symbol length. Delimiting characters such as spaces which precede a sequence of characters corresponding to a primary token are indicated by setting one data symbol in each primary token to a predetermined value. Sequences of capitalized characters are indicated by predetermined command tokens.

Abstract: An interactive method for composing an alphanumeric message by a caller using a telephone keypad includes storing (215) a lexical database (135) from which unigram probabilities, forward conditional probabilities, and backward conditional probabilities for a plurality of words can be recovered; storing a received sequence of key codes (405) representing a sequence in which keys on a telephone style keypad are keyed; generating a word trellis including candidate words (415) derived from the sequence and the lexical database; determining a most likely phrase (420) from the candidate words, the unigram probabilities, forward conditional probabilities, and backward conditional probabilities; generating a most likely message (425) from the most likely phrase and presenting the most likely message to the caller; and confirming that the most likely message is the alphanumeric message (430).

Abstract: A method and apparatus are for receiving a portion of a message by a call receiver (2). A radio signal is intercepted (910) which is modulated with a hierarchical signalling protocol having variable bit rate protocol divisions (443). A particular variable bit rate protocol division (443) includes the portion of the paging message and a bit rate indicator (460). An optimum bit rate that is being used in the particular variable bit rate protocol division is determined (930) from the bit rate indicator (460). Words (450, 455) in the particular variable bit rate protocol division (443) are decoded (940) using the optimum bit rate. The portion of the paging message is obtained (950) from the words.

Abstract: A radio communication system (5) includes transmitting unit (1) coupled to at least one controller (6). The controller (6) is adapted to combine message intervals (208) into a plurality of arrangements, each arrangement having a selected number of message intervals (208). An arrangement is then selected, and included in an acquisition group message. The arrangement is used for directing a number SCRs (selective call receivers) (2) targeted to receive the acquisition group message to monitor messages during the message reception interval (203) according to the arrangement. The controller (6) then invokes the transmitting unit (1) to transmit the acquisition group message to the SCRs (2). Messages targeted for specific SCR's (2) are then generated, and transmitted by way of transmitting unit (1) during the message reception interval (203) according to the arrangement selected. The targeted SCRs (2) intercept the messages according to the arrangement received in the acquisition group message.

Abstract: A selective call receiver (800), including a receiver circuit (101) and a processor (810), is used for synchronizing an internal reference to symbol edges of a plurality of symbols in a multi-level radio signal transmitted by a radio communication system. To perform this function the processor (810) is adapted to cause the receiver circuit (101) to demodulate the multilevel radio signal to in-phase and quadrature signals (108, 106), convert the in-phase and quadrature signals (108, 106) to a sequence of state transitions representative of the plurality of symbols, detect at least one same state transition from the sequence of state transitions, and synchronize the internal reference to the at least one symbol edge of the plurality of symbols based on the at least one same state transition.

Abstract: A digital demodulator (100) for use in a communication device comprising a mixer (110) which samples a limited IF signal derived from a received radio frequency (RF) signal at a rate less than a Nyquist rate of the limited IF signal and generates a resulting IF signal. A continuous integrator (130) is connected to the mixer (110) and integrates the resulting IF signal over a predetermined number of samples thereof to generate a numerical value representative of a modulation frequency of a limited IF signal. An adaptive peak-valley bit slicer (150) is connected to the continuous integrator (130) and compares each numerical value with a peak threshold, a valley threshold and a mid threshold and generates most-significant-bit (MSB) and least-significant-bit (LSB) values for each sample. The adaptive peak-valley bit slicer (150) adjusts the peak and valley thresholds for use in determining a level of a current numerical value based on the LSB and MSB values determined for a prior sample of the numerical value.

Abstract: A clock recovery circuit for recovering a symbol clock (226) includes a level decoder (210) for determining one of a plurality of received states of a demodulated signal (105) during each symbol period of the symbol clock (226). Each of the plurality of received states corresponds to one of at least two modulation levels. The level decoder (210) generates for each of the plurality of received states a sign signal (212) having transitions at central threshold transition times and a magnitude signal (211). An edge selector (220) determines selected central threshold transition times. A synchronizable clock (225) is synchronized by the selected central threshold transition times, resulting in a significant reduction of symbol clock (226) jitter.

Abstract: A low input prescaler (800) that is responsive to input signals having low amplitude alternating current (AC) components includes a switched tunable prescaler (280) that generates a prescaler output signal (221) having a prescaler output frequency during an operational state of the prescaler and having a free-running frequency that is responsive to a tuning control signal (216) during a tuning state of the prescaler. A frequency comparator (235) generates a comparator output in response to a difference between a reference frequency and the prescaler output frequency. A prescaler tuner (290, 390) adjusts the tuning control signal in response to the comparator output during the tuning state to minimize the difference between the reference frequency and the prescaler output frequency, and holds the tuning control signal during the operational state. The prescaler is used in phase lock loops (200, 400, 600) and other circuits.

Abstract: A method for selectively marking integrated circuit chips (205, 210) formed on a wafer (200) includes the steps of testing the integrated circuit chips (205, 210)) of the wafer (200) to determine whether the integrated circuit chips (205, 210) are functional, dispensing underfill material (215) only on functional integrated circuit chips (205), and separating, subsequent to the dispensing step, the wafer (200) into individual integrated circuit chips (205, 210). The functional integrated circuit chips (205) are marked with the underfill material (215), while nonfunctional integrated circuit chips (210) are not marked with the underfill material (215).