Abstract: The subject parity circuit generates a single parity bit for a prescribed DATA SET. The DATA SET comprises n bytes which are simultaneously transmitted to the parity circuit over n data transmission leads. The n bytes are simultaneously combined bit by bit to determine whether an odd or even number of bits have been received. A cummulative sum is determined, and the single parity bit is generated with the receipt of the last n bits of the DATA SET.

Abstract: The subject telephone switching provides for the redirection of established data calls to remotely located digital terminals and the reservation of these digital terminals at the time a data call is originated. In particular, a user can originate a data call from a telephone station set, reserve a selected digital terminal which may or may not be colocated with the telephone station set, and at some point in the call, transfer the established data call to the selected digital terminal by operating a data button on the calling telephone station set.

Abstract: The digital terminal keyboard dialing arrangement of this invention enables a user to originate data calls directly from any digital terminal keyboard without requiring the use of an associated telephone station set. In particular, the subject telephone switching system has a control signalling channel between the digital terminals and the system processor. This control signalling channel is used to convey the ASCII output from the digital terminal keyboard directly to the system processor on a call origination. Upon call completion, the ASCII output from the digital terminal keyboard is routed to the called party via the switching network.

Abstract: This data call transfer arrangement enables a calling party to originate a data call from a telephone station set and then transfer the data call to one of a number of predefined digital terminals. This is accomplished by operating the DATA button on the telephone station set corresponding to the selected digital terminal once the data call is established. This action causes the subject telephone switching system to replace the telephone station set on the call appearance with the selected digital terminal.

Abstract: The subject device control system provides a new method of determining when resource consuming loads are to be disabled to prevent the total resource consumption from exceeding a predetermined threshold. This system bases the decision making process on past consumption, past load shedding activity and predicted future load activity. The controlling algorithm is applied to the present resource consuming situation for a plurality of different time interval configurations and the worst case result of these computations is used to control the load shedding.

Abstract: The subject switchhook status detector is part of a battery feed circuit and functions to sense the magnitude of the current flowing on both the tip and ring conductors. The detector also generates a sum signal which represents the total metallic current flowing in the loop. The subject detector maintains the battery feed circuit in the off state until the sum signal exceeds a first predetermined threshold and, concurrently, both the tip and ring currents individually exceed another predetermined threshold. This combination of requirements prevents the generation of erroneous off-hook indications.

Abstract: In a data processing system, the subject error correcting circuit is connected in the bridging mode to the data bus which interconnects a processor and a memory for error detection. It is presumed that the memory words obtained from the memory are relatively error-free, and the subject circuit does not delay their transmission, but simply monitors the data. If an error in the data is detected, an error signal is generated on the next processor microcycle, the processor aborts its present operation and then fetches the corrected data from the error correction circuit. If the frequency of errors increases or if a permanent error is detected, the subject error correction circuit switches to an in-line mode where it functions much as prior art error correction circuits: delaying the transmission of each memory word until the error check is complete.

Abstract: The subject channel interface circuit functions in a multiprocessor environment to provide a high speed interface between a processor and the communication channel which interconnects all the processors. The communication channel carries data messages, which messages contain a header field specifying source, destination and control information. The subject channel interface circuit is programmable and serves to dynamically translate the header portion of the data message as it is received and thereby determine whether this data message is to be stored in the processor memory. If the data message is to be stored, the channel interface circuit immediately converts the header field into a hardware address, which is used to activate a specific location in processor memory. The data message is then inputted (via DMA) to this memory location and the appropriate buffer pointers are reset.

Abstract: The battery feed circuit of the present invention does not rely principally on balanced current generation circuitry but, instead, uses a feedback circuit to ensure the production of the required currents on the communication pair. The subject feedback circuit automatically and instantaneously compensates for longitudinal currents by precisely sensing the currents appearing on each lead of the communication pair. These sensed currents are summed to remove the balanced longitudinal component and the resultant signal represents the actual metallic current on the communication pair. This actual metallic current is subtracted from a predetermined reference current and the difference between these two signals constitutes an error signal which is amplified to provide the current drive supplied to the communication pair.

Abstract: The subject gyrator circuit is realized by a single amplifier and six resistors, which resistors are selected to satisfy a single equation. This permits great flexibility in setting the Z.sub.12 and Z.sub.21 impedance values without affecting the stability of the basic circuit.

Abstract: The disclosed energy control system employs the serving electronic stored program PBX to regulate the operation of energy consuming devices located throughout a hotel/motel or office building in accordance with one or more modes of operation as offered by an algorithm stored in the PBX memory. This is accomplished by equipping each guest room or office with a control circuit to regulate the operation of the energy consuming devices located in that room. These control circuits are activated by the presence of an audio frequency tone on the telephone line associated with the room. To minimize the impact of this scheme on the traffic capacity of the PBX time division switching network, all activated control circuits are concurrently connected to a single time slot, which supplies the required audio frequency tone.

Abstract: The subject electronic device packaging arrangement is designed to enhance heat transfer from an electronic device to the printed circuit board to which it is attached. This is accomplished by employing a thermally conductive base having a depression in the top thereof into which the electronic device is placed and bonded. The base has a protuberance in the bottom thereof corresponding to the depression in the top, which protuberance is attached to the associated printed circuit board. The protuberance on the base is formed to be in contact with the printed circuit board surface to provide thermal dissipation into the board by conduction processes. Continuous or segmented conductors are bonded both to the electronic device and to the base. These conductors are bent over the edge of the base to the bottom of the base where they align with corresponding contact points on the printed circuit board.

Abstract: The disclosed microprocessor support system provides a total "laboratory" environment for developing and testing application software as well as for debugging the microprocessor-based application machine itself. The microprocessor support system contains a time shared minicomputer equipped with a full set of peripherals which functions as the main or operating system. A data link connects this operating system with test equipment located at the site of the application machine. This test equipment consists of a field test unit which provides an interface between the application machine, a local keyboard terminal and the operating system such that an engineer at the site of the application machine has access through the field test unit to both the microprocessor-based application machine and the operating system with its sophisticated hardware and software resources to assist in developing and testing application software, as well as debugging the application machine itself.

Abstract: The disclosed signal multiplexing circuit (110) makes use of a single pair of wires (T, R) to interface a data and voice communication circuit such as an electronic key telephone (EKT) station set (100) with a central data and voice communication system such as a communication system (BCS). The signal multiplexing circuit transmits outgoing standard voice signals, outgoing auxiliary signals and outgoing data and, in turn, simultaneously receives incoming standard voice signals, incoming data and incoming auxiliary signals on the single pair of wires. Both time division and frequency separation techniques are concurrently employed to achieve multiple use of the single pair of wires without crosstalk between the plurality of signals. The data signals are transmitted as bipolar bit pairs preceded by a data start pulse pair. The outgoing data bipolar bit pairs are delayed until the center transition of the incoming data bipolar pulse pair is detected.

Abstract: The disclosed signal multiplexing circuit makes use of a single pair of wires to interface a data and voice communication circuit such as an electronic key telephone (EKT) station set with a central data and voice communication system such as a business communication system (BCS). The signal multiplexing circuit transmits outgoing standard voice signals, outgoing data and outgoing auxiliary signals and, in turn, simultaneously receives incoming standard voice signals, incoming data and incoming auxiliary signals on the single pair of wires. Both time division and frequency separation techniques are concurrently employed to achieve multiple use of the single pair of wires without crosstalk between the plurality of signals. The data signals are transmitted as bipolar bit pairs preceded by a data start pulse pair. The transmission of an outgoing data bipolar pulse pair is delayed until the incoming pulse pair has cleared the line, thus separating incoming and outgoing data in time.

Abstract: The disclosed signal limiting circuit is bridged on to a bidirectional communication path (T, R) and functions to selectively attenuate excessive signals (2V.sub.A) being transmitted in a predetermined direction on the bidirectional communication path. This is accomplished by a signal discriminator circuit (100) which separates the excessive signal (2V.sub.A) from the plurality of signals appearing on the communication path (T, R). The signal discriminator circuit (100) also inverts the isolated excessive signal, passes it through an attenuator (102) to a signal injection circuit (103) which injects a controlled amount of the 180 degrees out-of-phase isolated excessive signal back on the communication path (T, R) to cancel out a portion of the excessive signal, thereby providing selective attenuation of the excessive signal.

Abstract: A sample and hold circuit is disclosed which employs a matched pair of operational amplifiers as a decoupling circuit to isolate the output of the sample and hold circuit from the sampling capacitor. Prior art decoupling circuits employ a simple isolation amplifier which has a tendency to charge the sampling capacitor with the isolation amplifier input bias and leakage currents. The disclosed decoupling circuit employs one of a pair of matched operational amplifiers as a self-compensating isolation amplifier which dynamically generates the bias and leakage currents found at its input while isolating the sample and hold output from the sampling capacitor. The other operational amplifier is connected in series between the isolation amplifier and the sample and hold output and functions to cancel the input bias current signal generated by the self-compensating isolation amplifier.

Abstract: A sample and hold circuit is disclosed which employs a matched pair of operational amplifiers as a decoupling circuit to isolate the output of the sample and hold circuit from the sampling capacitor. Prior art decoupling circuits employ a simple isolation amplifier which has a tendency to charge the sampling capacitor with the isolation amplifier input bias and leakage currents. The disclosed decoupling circuit employs one of a pair of matched operational amplifiers as a compensation circuit to dynamically generate the bias and leakage currents found at the input of the other operational amplifier, which is employed as the sample and hold isolation amplifier. Thus, the net quiescent current into the input of the decoupling circuit is zero, thereby eliminating the capacitor charging problem of prior art isolation amplifiers.

Abstract: A thyristor switching network is disclosed in which the switching network control provides both crosspoint audit and centralized control capabilities. The switching network control circuit contains three signal generators each of which generates a particular control signal when enabled. A distribution circuit is also provided to connect each of the signal generators to a corresponding terminal of a selected thyristor crosspoint element. In this manner, the signal generators directly control the voltage appearing at any terminal of any crosspoint element and can be used to turn on, turn off, or audit the busy/idle status of any selected thyristor crosspoint element. Also, the thyristor crosspoints are switched on in the zero voltage mode and the dV/dt across the selected thyristor crosspoint element is controlled by the signal generators to eliminate false firing of the thyristor crosspoints.

Abstract: A semiconductor switching network is disclosed in which complementary bipolar transistors are employed as "floating" crosspoints. Each crosspoint consists of a pair of complementary bipolar transistors with each transistor being connected in series with one of the leads of the communication pair. Each one of the complementary bipolar transistors is, in turn, surrounded by a "protective control shell" of diodes and transistors which provides the crosspoint with overvoltage and reverse voltage protection and secures crosspoint turn-off. Additionally, the protective control shell contains a self-bias arrangement to eliminate the need for external power supplies to operate the crosspoint as well as an optoisolator control circuit to eliminate direct connections to external control circuits.