Abstract: A multiple layer tape bonding technique interconnects an integrated circuit chip having signal and ground bonding pads located thereon to other electrical devices. The tape bonding structure is comprised of a first layer having electrically isolated individual signal conductors coupled to respective ones of the signal bonding pads. The individual signal conductors extend away from the integrated circuit chip in an approximately parallel-spaced relationship to one another. An electrically insulating layer having a predefined thickness is deposited atop and adjacent the first layer. A ground plane layer overlies the insulating layer. The ground plane layer is comprised of a plurality of individual ground conductors coupled to respective individual ones of the ground bonding pads of the integrated circuit chip. The individual ground conductors overlie the insulating layer in a precisely spaced parallel relationship to the corresponding individual signal conductors.

Abstract: An applique of a prepatterned film of alpha particle resistant material, such as polyimide, is applied to a semiconductor wafer. The prepatterned film covers only the critical areas e.g. those affected by alpha particle impingement. Bond pads and scribe streets are not covered by the applique.

Abstract: An apparatus for quality control testing of semiconductor packages comprises a support platform for holding a device in a fixed location and a reciprocatable brush which is mounted to contact the device with a constant force. The reciprocating mechanism basically moves the brush horizontally across a test package but is linked with a cam system for elevating the brush out of contact with the test package during one of the strokes and lowering the brush back into contact with the test package during the other stroke. Highly accurate and repeatable abrasion tests can thus be performed.

Abstract: A method for stripping an organic photoresist layer from a semiconductor device comprises oxidation of the photoresist layer with oxygen plasma and subsequent removal of residual sulfur species using a fluorine-containing plasma.

Abstract: An improved lift-off process for forming metallized interconnections between various regions on a semi-conductor device relies on the use of a particular polyimide in forming a protective mask over the device. The polyimide is a copolymer of an aromatic cycloaliphatic diamine and a dianhydride which allows the resulting structure to withstand particularly high temperatures in the fabrication process. In particular, the polyamide when subjected to high temperature metallization under vacuum remains sufficiently soluble to be substantially completely removed from the device by immersion in common organic solvents. This allows high temperature metallization as interconnects for integrated circuits.

Abstract: A method for forming multiple conductive interconnect layers on a semiconductor device comprises defining a first conductive metal layer, applying a first insulating layer thereon, planarizing the first insulating layer by etching a sacrificial planarization layer, applying a second insulating layer, forming vias through first and second insulating layers and applying a second conductive layer thereon. Optionally, a third insulating layer can be applied over the first two and stepped vias formed to improve the interconnection of the first and second layers. The method reduces metallization failure associated with irregularities in the intermediate insulating layers.