Abstract: A procedure for planarizing a group II-VI composition which includes a resist and etch-back procedure wherein a thick resist coating relative to the degree of non-planarity is spun over a non-planar group II-VI layer to provide a planar resist surface. The resist is then etched back to the group II-VI layer with etching of both the resist and the group II-VI layer then continuing simultaneously and at substantially the same etch rate until all of the resist has been removed. The etching takes place in a chamber having a parallel plate RF plasma etcher using a dry etchant which uses the RF plasma. The etchant is a hydrogen and oxygen combination at low pressure which is activated by the RF excitation. An inert gas, preferably argon, and methane can optionally be added to the gas flow. The flow rate at each inlet is continuously adjustable. The flow of gas into the chamber continues while the chamber is also being pumped simultaneously to maintain the desired pressure within the chamber.
Abstract: A metal-to-polysilicon capacitor, a floating-gate transistor containing such a capacitor, and a method for making the same is disclosed. The bottom plate of the capacitor is formed over a field oxide structure, and the multilevel dielectric is deposited thereover. The multilevel dielectric is removed from the capacitor area, and an oxide/nitride dielectric is deposited over the exposed bottom plate and over the multilevel by way of LPCVD. A first layer of titanium/tungsten is preferably deposited prior to contact etch, and the contacts to moat and unrelated polysilicon are formed. Metallization is sputtered overall, and the metal and titanium/tungsten are cleared to leave the metallization filling the contact holes, and a capacitor having a titanium/tungsten and metal top plate.
Abstract: There is disclosed a manufacturing method and apparatus which allows for the efficient assembly of the exposure module of a xerographic reproduction system. The system uses an array of deformable mirrors fabricated in one embodiment, on a monolithic silicon substrate as a light modulation element. The substrate package is positioned with respect to a set of molded support brackets such that a multi-axis adjustment of this single element allows for the alignment of the entire optical set. A system of cameras is used, in conjunction with a computer, to control the substrate positioning and to determine optimum efficiency of the system. The computer adjusts the package around the various rotational axis in sequential fashion.
Abstract: DRAM cells and arrays of cell on a semiconductor substrate, together with methods of fabrication, are disclosed wherein the cells are formed in pairs or quartets by excavating a trench or two trenches through the cell elements to split an original cell into two or four cells during the fabrication. The cells include vertical field effect transistors and capacitors along the trech sidewalls with word lines and bit lines crossing over the cells.
Abstract: First and second EEPROM cells have first and second source regions (28a, 28b) formed in a semiconductor layer (12) to be of a second conductivity type opposite the first conductivity type of the layer and to be spaced apart from each other. A field plate conductor (100) is insulatively disposed adjacent, and defines, an inversion region (102), and further is laterally spaced between the first and second source regions (28a, 28b). The inversion region (102) is inverted from the first conductivity type to the second conductivity type upon application of a predetermined voltage to the field plate conductor (100). First and second channel regions (48a, 48b) are defined between the respective source regions (28a28b) and the inversion region (102) and each include floating gate and control gate subchannel regions (60a, 62a, 62b, 60b). First and second floating gate conductors (40a, 40b) are insulatively disposed adjacent respective floating gate subchannel regions (60a , 60b) to control their conductance.
Abstract: Hot-electron-induced degradation of a semiconductor device (10) is reduced by converting the silicon surface (18) to a fluorinated-silicon compound interface region (23). The fluorinated-silicon compound interface region (23) is formed by etching the device (10) in a fumer (30) using anhydrous hydrofluoric acid. After a sacrificial oxide is grown over the silicon surface (18), the device (10) is placed in a container (32). A mixture of nitrogen, moistened nitrogen and nitrogen/anhydrous hydrofluoric acid is injected into the container (32) to conduct the etch. The anhydrous hydrofluoric acid converts the silicon to a fluorinated-silicon compound, such as H.sub.2 SiF.sub.6, and water. The fluorinated-silicon compound interface region (23) has stronger molecular bonds than the typical hydrogen-silicon formed at the oxide/silicon interface and is, therefore, less likely to be broken apart by hot-electrons.
Abstract: A T-shaped trench intersection shaped to make uniform the wall-to-wall spacing at the trench intersection and prevent the formation of voids when the trench is filled with a conformal insulating material.
Abstract: A monochrome image becomes expanded into a color image for storage in a bit mapped color display memory. The color expand operation substitutes color data of one of two designated colors for the "1" or "0" monochrome data of a stored monochrome image. The first color code is substituted for all pixels of the monochrome image represented by a "1" and the second color code is substituted for all pixels of the monochrome image represented by a "0". This color expanded image is then stored in the color display memory which controls the color picture shown to the user. This technique permits storage of commonly used images such as alphanumeric characters of various fonts or icons in a compressed form with one bit per pixel. These images are formed in color using the color expand operation at the time of drawing into the color display memory. Otherwise these images would need to be stored in multiple bit per pixel color form for all desired colors requiring considerable memory for redundant data.
April 6, 1990
Date of Patent:
March 10, 1992
Texas Instruments Incorporated
Karl M. Guttag, Michael D. Asal, Mark F. Novak, Thomas Preston
Abstract: A TTL compatible CMOS high-speed lower-power supply-independent input buffer has a first current mirror which supplies current to a reference node of the input buffer when the signal at the input node of the buffer goes to a high state. An MOS transistor has its gate connected to the input node and switches hard on when the input node goes to a high level, pulling the reference node to a low level. A second current mirror is provided which injects current into the reference node for a predetermined period of time after the voltage level at the input of the buffer goes to a low level to pull the reference node to a high level. Both the first and second current mirror are switched on only during transition states of the input buffer, to minimize power dissipation when the input buffer is in its quiescent state.
Abstract: A television receiving system includes a digital unit, which has at least one single-instruction multiple-data processor, especially suitable for television processing. The processor receives data samples fo each horizontal line word-serially, but processes the line in parallel. The processor has input, computational, and output layers that operate concurrently. Internal register files emulate line memory to eliminate the need for external line memories. The processor may be programmed with various improved definition television tasks, downloaded to it from a host development system. Field memories and multiplexers control the data flow so that a still picture may be displayed.
Abstract: A heterostructure field effect transistor having a buffer layer comprising a first compound semiconductor material. A layer of second semiconductor material different from the first material is formed over the buffer layer. The second layer has a total thickness less than 250 .ANG.. A doped third semiconductor layer formed over the second layer. The net has a dopant concentration in the second layer is greater than the net dopant concentration in the third layer. A gate layer is positioned over the third layer. In a preferred embodiment the second layer is a pulse-doped pseudeomorphic material. There is also provided a method for making the heterostructure field effect transistor. A doped pseudomorphic semiconductor layer of a first conductivity type is formed between first and second other semiconductor layers, the second layer including a net dopant concentration of the first conductivity type. A Schottky gate electrode is formed in contact with the second layer.
Abstract: An advanced video processor generates displays for displaying of either graphics or text information via a display monitor or a TV set operating as a monitor. A color palette is included in the advanced video processor for programming of the color of the display. The color palette provides 512 color selections, any sixteen of which may be displayed at once.
Abstract: A method for preparing a germanium layer (22) adjacent to a germanium silicon layer (20). Initially, a P-germanium silicon layer (16) is deposited on to an N-germanium silicon layer (14). The continuous germanium layer (22) is formed by heating the layers (14 and 16) in a steam oxidation step to approximately 1000 degrees Centigrade to transform the P-germanium silicon layer (16) into the P-germanium layer (18) and a SiO.sub.2 layer (22). A method for forming a heterojunction bipolar transistor utilizing a P-germanium layer (50) is also disclosed.
Abstract: A device for tracking an object (12) in three dimensional space is provided which comprises a fiber optic sensor array (14). Fiber optic sensor array (14) comprises a row plane (16) and a column plane (18) each comprising a plurality of parallel optical fibers bonded together. A row detector (20) is coupled to the ends of the fibers comprising row plane (16). A column detector (22) is coupled to the ends of the fibers comprising column plane (18). Row and column detectors (20) and (22) are coupled to a decoder circuit (24). First and second beam generators (26) and (28) are affixed to the object (12) and are each operable to transmit beams (30) and (32) which terminate on the fiber optic sensor array (14). By determining the points of incidence of beams (30) and (32), the decoder circuit (24) may determine the position of the object (12) in three dimensional space.
Abstract: A method for applying a dielectric material to a solar array having an edge, a light gathering side and a backside, which includes the steps of sealing the array along the array edge, providing a gas pressure differential between the light gathering side and the backside which pressure is greater on the light gathering side than on the backside and applying the dielectric material to the backside of the array wherein the gas pressure differential is sufficient to substantially prevent the dielectric material from leaking from the backside to the light gathering side.
Abstract: A memory cell system is disclosed with properties of asymmetrical operation such that the occurrence of memory error due to certain environmental disturbances is detectable. The asymmetry of operation can be adjusted to set the level at which the disturbance is detected. Detection of memory error in the system can be used to shut off access to an associated memory array in order to prevent error in the array.
Abstract: A test cell (12) provides boundary scan testing in an integrated circuit (10). The test cell (12) comprises two memories, a flip-flop (24) and a latch (26), for storing test data. A first multiplexer (22) selectively connects one of a plurality of inputs to the flip-flop (24). The input of the latch (26) is connected to output of the flip-flop (24). The output of the latch (26) is connected to one input of a multiplexer (28), the second input to the multiplexer (28) being a data input (DIN) signal. A control bus (17) is provided for controlling the multiplexers (22, 28), flip-flop (24) and latch (26). The test cell allows input data to be observed and output data to be controlled simultaneously.
Abstract: A plasma flow is uniformly distributed over the surface of a water (76) by an L-shaped tube (64) and a distribution ring (62). A dispersal gas, which may either comprise an inert gas or a gas that cooperates with the reactive species of the plasma, is sprayed from the tube (64) and the ring (62) into the flow of the plasma. The ring (62) comprises a hollow tube encircling the outlet of a plasma reactor. A gas is circulated through the ring (62) within the hollow interior (66) and is emitted therefrom by nozzles (70). The tube (64) comprises a quartz or anodized aluminum L-shaped tube which is positioned directly in the flow of the plasma. The gas is emitted from the tube (64) in a direction directly opposite and into the flow of the plasma.