Abstract: A system scan path architecture is provided by a device select module (DSM) (18) which may be used in conjunction with associated circuits (16a-b) to select secondary scan paths (PATH1-m) on each circuit for coupling with a primary scan path on a test bus (14). The test bus (14) is controlled by a primary bus master (12). Remote bus masters (124) may be used in conjunction with the DSMs (18) to provide serial-scan testing independent of the primary bus master (12).

Abstract: A communication receiver (12) is provided having a radio frequency section (20) for receiving a communication signal (14) and a corresponding code signal (16) carrying an identification code. An intermediate frequency section (26) is coupled to radio frequency section (20) to convert the frequency of said communication signal. A decoder (42) having a memory for storing a security code, is coupled to radio frequency section (20) and intermediate frequency section (26). Decoder (20) is operable to compare the identification code and the security code and selectively disable the intermediate frequency section in response.

Abstract: Vertical buried emitter heterojunction bipolar transistors having greatly reduced emitter to base junction area and collector dimensions are fabricated in a gallium arsenide substrate to form an integrated circuit structure. The ability to scale these critical dimensions is made possible by forming a portion of the base along the side walls and bottom of a trench which has been etched in the upper two layers of a layered gallium arsenide structure. The base is formed by implanting beryllium into the surface of an upper layer, the trench sidewalls which are formed in an undoped layer, and the bottom of the trench which is an undoped layer formed on the buried emitter. A GaAs collector layer having reduced lateral dimensions is deposited in the trench and in part, on the surface of the layered structure. Since only a small portion of the base region (the bottom of the trench) is in direct contact with the heavily doped emitter layer, the emitter to base junction area can be significantly reduced.

Abstract: A device having a circled array of tapered motor driven rollers center and find the flat edge of a semiconductor wafer by rotating the wafer until the flat edge is over a photo cell, at which time finder rollers secure the wafer in its centered and orientated position.

Abstract: A method for preventing single event upsets (SEUs) in MOS circuits is disclosed. A resistive area (88, 89) is situated in a semiconductor device such that when a high energy particle passes through the device and the resistive area (88, 89) the stray carriers caused by the particle will pass through the resistive area (88, 89) causing a voltage drop which will prevent the upset of the MOS circuit. A low resistance path is provided for the normal operating current in the device so that the normal operating parameters of the device are not affected by the protection provided by the resistive area (88, 89).

Abstract: One embodiment of the invention provides an EPROM and a method of fabricating an EPROM with enhanced capacitive coupling. Trenched memory cells each comprise a pleat-shaped floating gate with the control gate nested in a fold of the floating gate to increase the coupling ratio with the control gate. As a result higher programming speed and improved cell density may be obtained for a given programming voltage. Formation of bit lines along trench walls results in lower bit line resistivity for a given cell density.

Abstract: A transponder arrangement is described comprising an interrogation unit (10) which sends an RF interrogation pulse to at least one responder unit (12). The responder unit (12) then transmits back data stored therein in the form of a modulated RF carrier to the interrogation unit (10). In the responder unit (12) is an energy accumulator (136) which stores the energy contained in the RF interrogation pulse. The responder unit (12) further contains means (142, 148) which in dependence upon the termination of the reception of the RF interrogation pulse and the presence of a predetermined energy amount in the energy accumulator (126) initiate the excitation of an RF carrier wave generator (130, 132, 134) operating with the frequency contained in the RF interrogation pulse.

Abstract: Preferred embodiments include encoders and encoding methods for encoding integers as sparse binary vectors as used in neural networks. The encoding is by position of nonzero components; such as for N component vectors, the integer n is represented by a sequence of n components equal to zero followed by a sequence of log.sub.2 N components equal to one and then a sequence of N-n-log.sub.2 N components equal to zero. Other preferred embodiments include permutations of vector components while retaining the same number of nonzero components and also with partitioning into more and less significant subvectors.

Abstract: A scanning electron microscope (SEM) (24), or other irradiating device, is used to create a potential in sample areas (39b) of a test structure (39) formed on the surface of an integrated circuit wafer. A conduction path between the irradiated sample area and a common area (39a) is detected via an ammeter (40) connected between the sample area (39b) and a voltage source (42). Monitoring circuit (44) produces an output indicative of those sample areas (39b) which are electrically coupled to the common area (39a).

Abstract: A system scan path architecture is provided by a device select module (DSM) (18) which may be used in conjunction with associated circuits (16a-b) to select secondary scan paths (PATHl-m) on each circuit for coupling with a primary scan path on a test bus (14). The test bus (14) is controlled by a primary bus master (12). Remote bus masters (124) may be used in conjunction with the DSMs (18) to provide serial-scan testing independent of the primary bus master (12).

Abstract: A contact-free floating-gate non-volatile memory cell array and process with silicated NSAG bitlines and with source/drain regions buried beneath relatively thick silicon oxide. The bitlines having a relatively small resistance, eliminating the need for parallel metallic conductors with numerous bitline contacts. The array has relatively small bitline capacitance and may be constructed having relatively small dimensions. Bitline isolation is by P/N junction or by oxide-filled trench, permitting relatively small spacing between transistors. Wordlines may be formed from silicided polycrystalline or other material with low resistivity. Coupling of programming and erasing voltages to the floating gate is improved by using an insulator with relatively high dielectric constant between the control gate and the floating gate. The resulting structure is a dense cross-point array of programmable memory cells.

Abstract: A method of preventing forward biasing of PN junctions in junction isolated semiconductor devices to prevent parasitic transistor action. A biasing element is connected to the substrate/isolation regions to switch the regions to a low potential. The method is particularly well suited for implementation in the new multi-epitaxial semiconductor processes and structures.

Abstract: A translucent hemispherical diffuser provides shadowless, uniform illumination of an object to be inspected or otherwise viewed. The optical medium of the translucent diffuser has a milk glass optical consistency, and/or one or more surfaces of the diffuser may be textured to diffuse light entering or leaving the optical medium of the diffuser. The hemispherical diffuser is placed between a light source and the object to be viewed. Light from the light source entering the optical medium of the diffuser is re-radiated uniformly from the concave surface of the diffuser. The object to be viewed is located approximately at the center of curvature of the hemispherical diffuser. Thus, the radiating concave surface of the diffuser subtends a solid angle of approximately two -pi steradians. Light may be scattered and diffused by various reflecting surfaces external to the diffuser, prior to entering the optical medium of the diffuser.

Abstract: The invention provides a bipolar transistor structure on a buried oxide layer for use in an integrated circuit and a method for fabricating the same. The invention may be incorporated into a method for fabricating bipolar transistors in a BiCMOS structure. The bipolar transistor is constructed in two stacked epitaxial layers. The first epitaxial layer is used to form both the MOSFET and the buried collector of the bipolar transistor. The second epitaxial layer is grown as a blanket epitaxial layer. The intrinsic collector and the base of the bipolar transistor are formed in the second epitaxial layer. An oxide layer is formed over the base. The emitter is formed of a polysilicon layer which is deposited through an opening in the oxide layer such that the polysilicon layer contacts the second epitaxial layer.

Abstract: A latch-up free CMOS structure and method of fabrication thereof is disclosed. A P-type substrate (40) is appropriately masked to form a plurality of sites in which isolated wells (50) are formed. A thermal oxide layer (56) is grown on the surface of each well (50), and a boron channel stop (62) implanted therearound. Polysilicon semiconductor material (68) is formed within each well, and implant doped to form an N-well (76) of material. The P-substrate (40) is planarized. PMOS transistors are formed within the oxide isolate N-wells (76), while NMOS transistors are formed in the P-substrate (40) outside the wells.

Abstract: A sensor system (50) for measurements of semiconductor wafer minority carrier lifetime. The sensor (50) includes a microwave source (78) for generating a plurality of microwave signals and a waveguide (52) for emitting the microwave signals in the direction of the semiconductor wafer (20) in a processsing chamber (18). A collector waveguide (84) detects the reflected microwave signals from the semiconductor wafer (20) and directs the microwave signals to and from the emitter waveguide (52) so as to generate a plurality of electrical signals relating to semiconductor wafer (20) physical properties. A photon energy source (102) intermittently emits photon energy in the direction of the semiconductor wafer (20). Based on the differing microwave reflectance measurements following the injection and removal of photon energy, process control computer (76) calculates semiconductor substrate physical characteristics.

Abstract: A method is provided for forming multiple layers of interconnection adjacent a planar surface. A first insulator layer is formed adjacent the selected planar surface. A first conductor layer is formed adjacent the first insulator layer. A second insulator is formed adjacent the first conductor layer. A first cavity and a second cavity are formed, each having sidewalls extending through said second insulator layer and said first conductor layer. The first cavity is formed wider than the second cavity. A third insulator layer is conformally deposited adjacent the second insulator layer, such that sidewall insulators are deposited on sidewalls of the first cavity and such that the second cavity is substantially filled with insulator. An etch is performed through the first cavity to expose a portion of the planar surface. A second conductor layer is conformally deposited adjacent third insulator layer such that second conductor layer extends through the first cavity to contact the planar surface.

Abstract: A method and apparatus is disclosed for the non-destructive measurement of die-attach quality in packaged integrated circuit. The apparatus is used in a production line and uses acoustical pulses to generate signals from within the integrated circuit indicative of the die-attach quality.

Abstract: A transistor (42) is provided having a gate conductor (44) formed adjacent a semiconductor substrate (46) and separated therefrom by a gate insulator (48). Sidewall spacers (52, 54) are formed at the sides of gate conductor (44) and adjacent semiconductor substrate (46). Diffused regions (56, 58) are formed within semiconductor substrate (46) in order to provide source/drain regions for transistor (42). Positive charges from radiation are trapped within sidewall spacers (52, 54) thereby attracting negative charges from semiconductor substrate (46) such that a negative charge layer is created between diffused region (56) and gate edge (50a) and also between diffused region (58) and gate edge (50b).

Abstract: A circuit (90) converts a true ECL signal to a true TTL signal. The circuit includes a differential circuit (180) that receives an ECL signal having high and low values. The differential circuit produces a differential signal therefrom that has a high value in response to one of the high and low values of the true ECL signal, and a low value in response to the other of the high and low values of the true ECL signal. A first translator circuit (36, 64) has an input (32) coupled to the differential circuit (180). The first translator circuit (36, 64) transmits a true low TTL output (56) signal having a voltage level referenced to the voltage level of a TTL low supply voltage in response to receiving a high value of the differential signal. A second translator circuit (46, 52) has an input (38) and is coupled to a TTL high supply voltage and the output (56).