Patents Represented by Attorney, Agent or Law Firm Jaquez & Associates
  • Patent number: 8350624
    Abstract: Biasing methods and devices for amplifiers are described. The described methods generate bias voltages proportional to the amplifier output voltage to control stress voltages across transistors used within the amplifier.
    Type: Grant
    Filed: September 1, 2010
    Date of Patent: January 8, 2013
    Assignee: Peregrine Semiconductor Corporation
    Inventor: Fleming Lam
  • Patent number: 8330504
    Abstract: Dynamic biasing methods and circuits are described. The described methods generate bias voltages that are continuously varied so as to control stress voltages across transistors used within a cascode stack.
    Type: Grant
    Filed: February 4, 2011
    Date of Patent: December 11, 2012
    Assignee: Peregrine Semiconductor Corporation
    Inventor: Chris Olson
  • Patent number: 8305139
    Abstract: Driver circuits and methods related thereto for driving high power and/or high frequency devices are described. The driver circuits comprise transistor stacks and capacitors coupled with the transistor stacks. Voltages across the capacitors depend on state (on or off) of each transistor in the transistor stacks. These voltages in turn determine output voltages generated by the driver circuits.
    Type: Grant
    Filed: October 5, 2011
    Date of Patent: November 6, 2012
    Assignee: Peregrine Semiconductor Corporation
    Inventor: Jeffrey A. Dykstra
  • Patent number: 8243423
    Abstract: An improved gangable meter center for distributing electric power to and measuring electric power consumption by a plurality of individually measured units in a complex comprises: a plurality of meters for measuring the electric power consumption by the plurality of individually measured units in the complex; and a plurality of feeder buses electrically coupled between at least one utility line supplying power to the plurality of individually measured units in the complex, wherein the plurality of meters are included within the meter center without use of a meter socket. Ganged meter centers comprise at least two such gangable meter centers.
    Type: Grant
    Filed: October 30, 2009
    Date of Patent: August 14, 2012
    Assignee: Eaton Corporation
    Inventors: Michael J. Ranta, Eric A. Samuelson, James L. Gehlbach, Paul D. Seff
  • Patent number: 8218294
    Abstract: A removable transformer system is described. The system comprises a switchboard structure, a removable transformer moveable into and out of the switchboard structure, and a transformer mounting and supporting assembly for supporting the removable transformer. During operation of the system, the removable transformer is horizontally displaceable along the supporting.
    Type: Grant
    Filed: March 17, 2010
    Date of Patent: July 10, 2012
    Assignee: Eaton Corporation
    Inventors: Mitchell Dean Fretwell, Hector Gabriel Dumaine, Earl Dean Sandefur
  • Patent number: 8174303
    Abstract: A level shifter, or method, producing a final output from a driver supplied by a high-side source driver providing VDD or common, and a low-side source driver providing common or VSS. A delay is introduced to prevent a source driver output at common from beginning to transition toward a supply rail until a delaying source driver at a rail begins transitioning toward common. The level shifter may be single-ended or differential, and the delaying source driver may be coupled to the same final output driver as is the delayed source driver, or may be coupled to a different final output driver. The level shifter may have a second level shifter front end stage, which may have high-side and low-side intermediate source driver outputs coupled by a capacitor, and/or may couple one of the supplies to all intermediate source drivers via a common impedance or current limit Zs.
    Type: Grant
    Filed: July 17, 2009
    Date of Patent: May 8, 2012
    Assignee: Peregreine Semiconductor Corporation
    Inventors: Tae Youn Kim, Robert Mark Englekirk, Dylan J. Kelly
  • Patent number: 8143935
    Abstract: A circuit and method for controlling charge injection in a circuit are disclosed. In one embodiment, the circuit and method are employed in a semiconductor-on-insulator (SOI) Radio Frequency (RF) switch. In one embodiment, an SOI RF switch comprises a plurality of switching transistors coupled in series, referred to as “stacked” transistors, and implemented as a monolithic integrated circuit on an SOI substrate. Charge injection control elements are coupled to receive injected charge from resistively-isolated nodes located between the switching transistors, and to convey the injected charge to at least one node that is not resistively-isolated. In one embodiment, the charge injection control elements comprise resistors. In another embodiment, the charge injection control elements comprise transistors.
    Type: Grant
    Filed: July 26, 2007
    Date of Patent: March 27, 2012
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Alexander Dribinsky, Tae Youn Kim, Dylan J. Kelly, Christopher N. Brindle
  • Patent number: 8131251
    Abstract: A monolithic integrated circuit (IC), and method of manufacturing same, that includes all RF front end or transceiver elements for a portable communication device, including a power amplifier (PA), a matching, coupling and filtering network, and an antenna switch to couple the conditioned PA signal to an antenna. An output signal sensor senses at least a voltage amplitude of the signal switched by the antenna switch, and signals a PA control circuit to limit PA output power in response to excessive values of sensed output. Stacks of multiple FETs in series to operate as a switching device may be used for implementation of the RF front end, and the method and apparatus of such stacks are claimed as subcombinations. An iClass PA architecture is described that dissipatively terminates unwanted harmonics of the PA output signal.
    Type: Grant
    Filed: August 7, 2006
    Date of Patent: March 6, 2012
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Mark L. Burgener, James S. Cable
  • Patent number: 8129787
    Abstract: A method and apparatus for use in improving the linearity characteristics of MOSFET devices using an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one exemplary embodiment, a circuit having at least one SOI MOSFET is configured to operate in an accumulated charge regime. An accumulated charge sink, operatively coupled to the body of the SOI MOSFET, eliminates, removes or otherwise controls accumulated charge when the FET is operated in the accumulated charge regime, thereby reducing the nonlinearity of the parasitic off-state source-to-drain capacitance of the SOI MOSFET. In RF switch circuits implemented with the improved SOI MOSFET devices, harmonic and intermodulation distortion is reduced by removing or otherwise controlling the accumulated charge when the SOI MOSFET operates in an accumulated charge regime.
    Type: Grant
    Filed: March 22, 2011
    Date of Patent: March 6, 2012
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Christopher N. Brindle, Michael A. Stuber, Dylan J. Kelly, Clint L. Kemerling, George P. Imthurn, Robert B. Welstand, Mark L. Burgener
  • Patent number: 8111104
    Abstract: Biasing methods and devices for power amplifiers are described. The described methods and devices use the power amplifier output voltage to generate bias voltages. The bias voltages are obtained using rectifiers and voltage dividers. The described biasing methods and devices can be used with class-E power amplifiers.
    Type: Grant
    Filed: January 25, 2010
    Date of Patent: February 7, 2012
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Joseph F. Ahadian, Vikas Sharma, Neil Calanca, Jaroslaw E. Adamski
  • Patent number: 8106711
    Abstract: A stacked pre-driver stage and a power amplifier including the stacked pre-driver stage are described. The stacked pre-driver stage comprises stacked pre-drivers arranged in series between a supply voltage and a reference voltage. Each pre-driver includes a pre-driving amplifier, together with MOS transistors. Each pre-driver is subject, in operation, to a voltage difference which is inferior to a maximum allowed use voltage of the MOS transistors with a largely reduced voltage drop across the regulator included in the power amplifier.
    Type: Grant
    Filed: November 12, 2009
    Date of Patent: January 31, 2012
    Assignee: Peregrine Semiconductor Coporation
    Inventors: Jaroslaw Edward Adamski, Vikas Sharma, Dan William Nobbe
  • Patent number: 8092237
    Abstract: An electrical coupling bar is described. The coupling bar includes an electrically insulating support with two parallel grooves and metallic strips engaged in the grooves. The metallic strips project out of the grooves with opposite interior faces delimiting a free engagement space. Further, the other surfaces of metallic strips of the coupling bar are covered for protection.
    Type: Grant
    Filed: November 23, 2010
    Date of Patent: January 10, 2012
    Inventors: Francis Geiser, Michel Braillard, Grégory Crausaz
  • Patent number: 8081928
    Abstract: An RF switching circuit adapted to cancel selected harmonic signals. An unwanted harmonic signal Sh1 at a selected harmonic frequency Fsh of an operating frequency Fo exists in a signal Si conducted by the switching circuit, possibly produced by the switching circuit due to conduction through a first nonlinear impedance Znl(1). A compensating harmonic signal Sh2 is therefore generated by conduction via a nonlinear impedance Znl(2). Znl(1) may be due to parasitic conduction by “off” switching elements, while Znl(2) may be due to conduction by an “on” FET. The amplitude and/or phasing of Sh2 may be adjusted by selecting components for a network coupling Znl(2) to the conducted signal Si, such that Sh2 substantially cancels Sh1 across a target range of input power.
    Type: Grant
    Filed: February 3, 2006
    Date of Patent: December 20, 2011
    Assignee: Peregrine Semiconductor Corporation
    Inventor: Dylan J. Kelly
  • Patent number: 7960772
    Abstract: An RF switch to controllably withstand an applied RF voltage Vsw, or a method of fabricating such a switch, which includes a string of series-connected constituent FETs with a node of the string between each pair of adjacent FETs. The method includes controlling capacitances between different nodes of the string to effectively tune the string capacitively, which will reduce the variance in the RF switch voltage distributed across each constituent FET, thereby enhancing switch breakdown voltage. Capacitances are controlled, for example, by disposing capacitive features between nodes of the string, and/or by varying design parameters of different constituent FETs. For each node, a sum of products of each significant capacitor by a proportion of Vsw appearing across it may be controlled to approximately zero.
    Type: Grant
    Filed: April 26, 2007
    Date of Patent: June 14, 2011
    Assignee: Peregrine Semiconductor Corporation
    Inventor: Robert Mark Englekirk
  • Patent number: 7961052
    Abstract: A novel RF power amplifier integrated circuit (PA IC), unit cell, and method for amplifying RF signals are disclosed. One embodiment of a PA IC includes at least two linear arrays comprising transistor device units, and at least one linear array comprising capacitors. The transistor device units include source nodes that are jointly coupled to a source bus, and selected gate nodes that are jointly coupled to a gate bus. First electrodes of the capacitors are also jointly coupled to the source bus, and second electrodes of the capacitors are jointly coupled to the gate bus. Each linear array comprising capacitors is disposed between at least two linear arrays comprising transistor device units. In one embodiment, the PA IC includes unit cells. In some embodiments, each unit cell comprises two transistor device units and one or more capacitors. The capacitors are disposed between the transistor device units.
    Type: Grant
    Filed: October 28, 2009
    Date of Patent: June 14, 2011
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Peter Bacon, Robert Broughton, Yang Li, James Bonkowski, Neil Calanca
  • Patent number: 7937062
    Abstract: A monolithic integrated circuit (IC), and method of manufacturing same, that includes all RF front end or transceiver elements for a portable communication device, including a power amplifier (PA), a matching, coupling and filtering network, and an antenna switch to couple the conditioned PA signal to an antenna. An output signal sensor senses at least a voltage amplitude of the signal switched by the antenna switch, and signals a PA control circuit to limit PA output power in response to excessive values of sensed output. Stacks of multiple FETs in series to operate as a switching device may be used for implementation of the RF front end, and the method and apparatus of such stacks are claimed as subcombinations. An iClass PA architecture is described that dissipatively terminates unwanted harmonics of the PA output signal.
    Type: Grant
    Filed: August 7, 2006
    Date of Patent: May 3, 2011
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Mark L. Burgener, James S. Cable
  • Patent number: 7910993
    Abstract: A method and apparatus for use in improving the linearity characteristics of MOSFET devices using an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one exemplary embodiment, a circuit having at least one SOI MOSFET is configured to operate in an accumulated charge regime. An accumulated charge sink, operatively coupled to the body of the SOI MOSFET, eliminates, removes or otherwise controls accumulated charge when the FET is operated in the accumulated charge regime, thereby reducing the nonlinearity of the parasitic off-state source-to-drain capacitance of the SOI MOSFET. In RF switch circuits implemented with the improved SOI MOSFET devices, harmonic and intermodulation distortion is reduced by removing or otherwise controlling the accumulated charge when the SOI MOSFET operates in an accumulated charge regime.
    Type: Grant
    Filed: July 10, 2006
    Date of Patent: March 22, 2011
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Christopher N. Brindle, Michael A. Stuber, Dylan J. Kelly, Clint L. Kemerling, George P. Imthurn, Robert B. Welstand, Mark L. Burgener
  • Patent number: 7890891
    Abstract: A method and apparatus are disclosed for use in improving the gate oxide reliability of semiconductor-on-insulator (SOI) metal-oxide-silicon field effect transistor (MOSFET) devices using accumulated charge control (ACC) techniques. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one embodiment, a circuit comprises a MOSFET, operating in an accumulated charge regime, and means for controlling the accumulated charge, operatively coupled to the SOI MOSFET. A first determination is made of the effects of an uncontrolled accumulated charge on time dependent dielectric breakdown (TDDB) of the gate oxide of the SOI MOSFET. A second determination is made of the effects of a controlled accumulated charge on TDDB of the gate oxide of the SOI MOSFET.
    Type: Grant
    Filed: September 14, 2006
    Date of Patent: February 15, 2011
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Michael A. Stuber, Christopher N. Brindle, Dylan J. Kelly, Clint L. Kemerling, George P. Imthurn, Robert B. Welstand, Mark L. Burgener, Alexander Dribinsky, Tae Youn Kim
  • Patent number: 7871276
    Abstract: An electrical coupling bar is described. The coupling bar includes an electrically insulating support with two parallel grooves and metallic strips engaged in the grooves. The metallic strips project out of the grooves with opposite interior faces delimiting a free engagement space. The coupling bar further includes metallic strip protection means covering the other faces of the metallic strips.
    Type: Grant
    Filed: September 24, 2004
    Date of Patent: January 18, 2011
    Inventors: Francis Geiser, Michel Braillard, Grégory Crausaz
  • Patent number: 7872533
    Abstract: A regulator with decreased leakage and low loss for a power amplifier is described. Switching circuitry is used to connect the regulator input bias to a bias control voltage when the power amplifier is to be operated in an on condition or to a voltage generator when the power amplifier is to be operated in an off condition.
    Type: Grant
    Filed: June 3, 2009
    Date of Patent: January 18, 2011
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Jaroslaw Adamski, Daniel Losser, Vikas Sharma