Circuit and method for controlling charge injection in radio frequency switches

A circuit and method for controlling charge injection in a circuit are disclosed. In one embodiment, the circuit and method are employed in a semiconductor-on-insulator (SOI) Radio Frequency (RF) switch. In one embodiment, an SOI RF switch comprises a plurality of switching transistors coupled in series, referred to as “stacked” transistors, and implemented as a monolithic integrated circuit on an SOI substrate. Charge injection control elements are coupled to receive injected charge from resistively-isolated nodes located between the switching transistors, and to convey the injected charge to at least one node that is not resistively-isolated. In one embodiment, the charge injection control elements comprise resistors. In another embodiment, the charge injection control elements comprise transistors. A method for controlling charge injection in a switch circuit is disclosed whereby injected charge is generated at resistively-isolated nodes between series coupled switching transistors, and the injected charge is conveyed to at least one node of the switch circuit that is not resistively-isolated.

Skip to: Description  ·  Claims  ·  References Cited  · Patent History  ·  Patent History
Description
CROSS-REFERENCE TO RELATED UTILITY AND PROVISIONAL APPLICATIONS Claims of Priority

This application is a Continuation-in-Part (CIP) of commonly assigned U.S. patent application Ser. No. 11/520,912, filed Sep. 14, 2006 now U.S. Pat. No. 7,890,891, entitled “METHOD AND APPARATUS IMPROVING GATE OXIDE RELIABILITY BY CONTROLLING ACCUMULATED CHARGE”, which claims the benefit under 35 U.S.C. §119 (e) of U.S. Provisional Application No. 60/718,260, filed Sep. 15, 2005; the cited application Ser. No. 11/520,912, filed Sep. 14, 2006, is a CIP of U.S. patent application Ser. No. 11/484,370, filed Jul. 10, 2006 now U.S. Pat. No. 7,910,993, entitled “METHOD AND APPARATUS FOR USE IN IMPROVING LINEARITY OF MOSFETS USING AN ACCUMULATED CHARGE SINK”, which claims the benefit under 35 U.S.C. §119 (e) of U.S. Provisional Application No. 60/698,523, filed Jul. 11, 2005; the present CIP application is also a CIP of the cited U.S. patent application Ser. No. 11/484,370, filed Jul. 10, 2006, now U.S. Pat. No. 7,910,993; and the present CIP application claims the benefit under 35 U.S.C. §119 (e) of U.S. Provisional Application No. 60/833,562, filed Jul. 26, 2006, entitled “CIRCUIT AND METHOD FOR CONTROLLING CHARGE INJECTION IN RADIO FREQUENCY SWITCHES”. The present CIP application is related to commonly assigned application Ser. No. 10/922,135, filed Aug. 18, 2004, which issued Oct. 17, 2006 as U.S. Pat. No. 7,123,898, and is a continuation application of application Ser. No. 10/267,531, filed Oct. 8, 2002, which issued Oct. 12, 2004 as U.S. Pat. No. 6,804,502, entitled “SWITCH CIRCUIT AND METHOD OF SWITCHING RADIO FREQUENCY SIGNALS”. Application Ser. No. 10/267,531, filed Oct. 8, 2002, which issued Oct. 12, 2004 as U.S. Pat. No. 6,804,502, claims the benefit under 35 U.S.C. §119 (e) of U.S. Provisional Application No. 60/328,353, filed Oct. 10, 2001. The present CIP application is related to each of the applications set forth above. All of the applications and issued patents set forth above are hereby incorporated by reference herein as if set forth in full.

BACKGROUND

1. Field

The present teachings relate to electronic switches, and particularly to a circuit and method for controlling charge injection in semiconductor-on-insulator (SOI) radio frequency (RF) switches.

2. Description of Related Art

Radio frequency (RF) switches for directing RF signals are found in many different RF devices such as televisions, video recorders, cable television equipment, cellular telephones, wireless pagers, wireless infrastructure equipment, and satellite communications equipment. As is well known, the performance of RF switches is controlled by three primary operating performance parameters: insertion loss, switch isolation, and the “1 dB compression point.” The “1 dB compression point” is related to, and is indicative of, the linearity performance of an RF switch. Linearity performance is also indicated by the levels of RF signal harmonics generated by an RF switch, particularly at high RF power levels. These three performance parameters are tightly coupled, and any one parameter can be emphasized in the design of RF switch components at the expense of others. A fourth performance parameter that is occasionally considered in the design of RF switches is commonly referred to as the switching time or switching speed (defined as the time required to turn one side of a switch on and turn the other side off). Other characteristics important in RF switch design include ease and degree (or level) of integration of the RF switch, complexity, yield, return loss and cost of manufacture.

Charge injection is a problem that may occur in switching circuits such as SOI RF switches. Charge injection occurs when an applied voltage, such as a gate bias voltage, is connected to a “resistively-isolated node” through a coupling capacitance. A resistively-isolated node is defined herein as a node that at some interval during operation is connected to other circuit elements only through very high resistance connections. For example, a resistively-isolated node may occur at a transistor channel node located between series-connected transistors when the transistors are in an OFF-state. The coupling capacitance through which charge injection occurs may be either a parasitic capacitance of a circuit element (e.g., gate-to-source capacitance in a transistor), or a capacitance associated with a capacitor. For example, a bias voltage applied to the gate of a transistor may be connected to a resistively-isolated source node of the transistor through the gate-to-source capacitance. In general, charge injection may be a problem for many types of switching circuits. In particular, charge injection is significantly deleterious to the performance properties of SOI RF switches. Further, teachings on prior art SOI RF switches do not address this problem, for reasons described in more detail hereinbelow. Consequently, a need exists for a novel circuit and method for controlling charge injection in SOI RF switches.

SUMMARY

A novel circuit and method for controlling charge injection in an SOI RF switch are disclosed. The SOI RF switch may comprise a plurality of switching transistors connected in series (referred to herein as “stacked” switching transistors) implemented as a monolithic integrated circuit (IC) on an SOI substrate. In one embodiment the SOI RF switch is fabricated on an Ultra-Thin-Silicon (“UTSi”) substrate, also referred to herein as “silicon on sapphire” (SOS). In another embodiment, the SOI RF switch is fabricated in silicon-on-bonded wafer technology.

In an embodiment according to the present disclosure, an SOI RF switch includes at least one stack comprising a plurality of switching transistors connected in a series circuit. Charge injection control elements are connected to receive injected charge from resistively-isolated nodes located between the switching transistors, and to convey the injected charge to one or more nodes that are not resistively-isolated. Optionally, the charge injection control elements may be connected to receive a control signal for switching the charge injection control elements between ON-states and OFF-states. In one embodiment, each switching transistor in a stack of the SOI RF switch has at least one charge injection control element operatively connected between a source node and a drain node of each switching transistor.

In one embodiment, the charge injection control elements comprise charge injection control resistors. In another embodiment, the charge injection control elements comprise charge injection control transistors connected to receive a control signal for switching the injection control transistors between and ON-state and an OFF-state. The charge injection control transistors are operated so that they are in the ON-state when the switching transistors are in an ON-state. When the switching transistors are switched from the ON-state to an OFF-state, the charge injection control transistors are switched from an ON-state to an OFF-state after a selected delay time interval, thereby allowing the injected charge to be conveyed to the least one node that is not resistively-isolated.

In one embodiment, a method for controlling charge injection includes: 1) causing charge injection to occur at resistively-isolated nodes located between the switching transistors; 2) conveying the injected charge via charge injection control elements to at least one node that is not resistively-isolated; and, 3) optionally switching the charge injection control elements from an ON-state to an OFF-state.

According to one embodiment of the method for controlling charge injection, the charge injection control elements may comprise charge injection control resistors. In another embodiment, the charge injection control elements may comprise charge injection control transistors.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A schematically illustrates an SOI RF switch circuit using stacked switching transistors.

FIG. 1B illustrates the effects of charge injection in an SOI RF switch circuit using stacked switching transistors.

FIG. 1C illustrates simulated data for the RF switch of FIG. 1A wherein the RF switch has recently been switched from an ON-state to an OFF-state.

FIG. 2 schematically illustrates an embodiment according to the present disclosure, including a charge injection control circuit.

FIG. 3 shows a schematic illustration of an embodiment according to the present disclosure, using resistors in a charge injection control circuit.

FIG. 4 shows a schematic illustration of an embodiment according to the present disclosure, using transistors in a charge injection control circuit.

FIG. 5 is a flow chart diagram illustrating a charge injection control method.

FIG. 6A is a simplified schematic of an improved SOI NMOSFET adapted to control accumulated charge embodied as a four terminal device.

FIG. 6B is a simplified schematic of an improved SOI NMOSFET adapted to control accumulated charge, embodied as a four terminal device, wherein an accumulated charge sink (ACS) terminal is coupled to a gate terminal.

FIG. 6C is a simplified schematic of an improved SOI NMOSFET adapted to control accumulated charge, embodied as a four terminal device, wherein an accumulated charge sink (ACS) terminal is coupled to a gate terminal via a diode.

FIG. 6D is a simplified schematic of an improved SOI NMOSFET adapted to control accumulated charge, embodied as a four terminal device, wherein an accumulated charge sink (ACS) terminal is coupled to a control circuit.

Like reference numbers and designations in the various drawings indicate like elements.

DETAILED DESCRIPTION

Throughout this description, embodiments and variations are described for the purpose of illustrating uses and implementations of the inventive concept. The illustrative description should be understood as presenting examples of the inventive concept, rather than as limiting the scope of the concept as disclosed herein.

The problems caused by charge injection in SOI RF switches may be described with reference to FIG. 1A. An SOI RF switch 100 comprises stacked switching transistors 111, 113, 115 and 117. As disclosed in commonly-assigned U.S. application Ser. Nos. 10/922,135 and 10/267,531, incorporated by reference hereinabove, RF switches using stacked switching transistors have many performance advantages over prior art RF switches, such as higher RF power capability and reduced generation of harmonics in the switched RF signal. Although four stacked switching transistors are shown in FIG. 1A, it will be apparent to persons skilled in the arts of electronic circuits that the present teachings apply to RF switches having an arbitrary plurality of stacked switching transistors.

As shown in FIG. 1A, a first channel node of the switching transistor 111 may receive an input RF signal from a node 101. A second channel node of the switching transistor 111 is operatively connected through a node 103 to a first node of the switching transistor 113. A second channel node of the switching transistor 113 is operatively connected through a node 105 to a first channel node of the switching transistor 115. A second channel node of the switching transistor 115 is operatively connected through a node 107 to a first channel node of the switching transistor 117. A second channel node of the switching transistor 117 is connected to a node 109, which may output an RF signal. Typically, the nodes 101 and 109 are connected to load impedances (not shown) having resistance values to ground on the order of 50 or 75 ohms.

Gate nodes of the switching transistors 111, 113, 115 and 117 are separately connected to gate resistors 121, 123, 125 and 127, respectively. As disclosed in U.S. App. Nos. 10/922,135 and 10/267,531, the gate resistors are included to enable voltage division of RF signals across the switching transistors, protect bias circuits, and prevent transmission of parasitic RF signals between the stacked switching transistors. In some embodiments, the resistance Rg of each gate resistor should be at least ten times larger than the RF impedance of the gate-to-drain capacitance Cgd of the switching transistor to which it is connected. The gate resistors 121, 123, 125 and 127 are jointly connected to a gate control line 119 to receive a gate control signal C1.

The operation and advantages of RF switches such as the SOI RF switch 100 have been previously disclosed, as for example in U.S. application Ser. Nos. 10/922,135 and 10/267,531. However, the charge injection problem and solution have not been previously disclosed. In the present example, as illustrated by FIG. 1A, charge injection may occur at the nodes 103, 105 and 107 in the following manner. For the present example, the switching transistors 111, 113, 115 and 117 comprise enhancement-mode n-channel Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs) with a threshold voltage of +0.3 V. The gate control signal C1 is varied between a voltage of +3.0 V wherein the switching transistors are ON, and a voltage of −3.0 V wherein the switching transistors are OFF.

When the gate control signal C1 changes from +3 V to −3 V, the voltage passes through the switching transistor threshold voltage +0.3 V. During this process, the switching transistors 111 and 117 will switch from ON to OFF without difficulty because the nodes 109 and 101 are connected to load resistors (not shown) and therefore have an average DC potential at approximately ground potential or 0 V. The first channel node of the switching transistor 111 and the second channel node of the switching transistor 117 will be at a DC bias voltage of approximately 0 V, and their respective gate nodes will be a voltage of −3 V. However, when the switching transistors 111 and 117 switch from ON to OFF, the nodes 103, 105 and 107 become resistively isolated, as defined hereinabove in paragraph 004. For this reason, charge injection through the gate-to-channel capacitances of the switching transistors 113 and 115 to the nodes 103, 105 and 107 will occur as the control signal C1 voltage moves from the threshold voltage of +0.3 to −3 V. The charge injection will tend to maintain the nodes 103, 105 and 107 at voltages that may be only slightly more positive than the control signal C1 voltage. This will prevent the channels of the transistors 103, 105 and 107 from achieving a highly depleted condition, which is required for proper operation of the SOI RF switch 100.

These effects are illustrated in FIG. 1B by simulated data for the SOI RF switch 100. When a control voltage 142 (C1) is switched from +3 V to −3 V, voltages 134, 136 and 138, on nodes 107, 105 and 103, respectively, follow the voltage 142 as described above. Voltages 132 and 140 on nodes 109 and 101, respectively, remain at 0 V because they are not resistively isolated.

Prior art teachings are not informed regarding the problem of charge injection as described above. The principal reason for this is that RF switches such as SOI RF switch 100 are typically used to switch RF signals of several volts AC amplitude. If some of the switching transistors are not in a strong OFF-state, the RF signals will cause breakdown effects in the switching transistors that are strongly turned OFF and therefore receive larger RF signal voltages. These breakdown effects remove the injected charge from the resistively-isolated nodes, thereby enabling the switches to operate after a time interval. However, the breakdown effects may have deleterious effects on the reliability of the switching transistors. Further, because the breakdown effects occur over a time interval, the performance of the RF switch is adversely affected during the time interval. In particular, during the time interval wherein the injected charge is not completely removed, the switch response becomes nonlinear, and undesirable RF harmonics may be generated by the SOI RF switch.

These deleterious effects are illustrated in FIG. 1C by simulated data for the SOI RF switch 100 that has been recently switched from the ON-state to the OFF-state. At a time 99.0000 microseconds, an RF signal 160 is applied at the node 101. RF signals 158, 156, 154 and 152 appear at nodes 103, 105, 107 and 109, respectively, due to parasitic coupling effects. Persons skilled in the electronic arts will recognize from the distorted waveforms seen in the RF signals 158, 156, 154 and 152 that significant nonlinear distortion is present during the time interval illustrated, which corresponds to a time when charge injection effects are present. These deleterious effects due to charge injection can be reduced or eliminated according to the teachings herein.

SOI RF Switch with a Charge Injection Control Circuit.

An embodiment of a charge injection control circuit to remove injected charge in an SOI RF switch is illustrated by FIG. 2.

In FIG. 2, an SOI RF switch 200 includes charge injection control elements 201, 203, 205 and 207 that comprise elements of a charge injection control circuit. A first and second channel node of the charge injection control element 201 are operatively connected to the nodes 101 and 103, respectively. A first and second channel node of the charge injection control element 203 are operatively connected to the nodes 103 and 105, respectively. A first and second channel node of the charge injection control element 205 are operatively connected to the nodes 105 and 107, respectively. A first and second channel node of the charge injection control element 207 are similarly operatively connected to the nodes 107 and 109, respectively. Optionally (e.g., as described below in reference to FIG. 4), the charge injection control elements 201, 203, 205 and 207 may be connected to a control line 209 to receive a control signal C2.

The charge injection control elements 201, 203, 205 and 207 receive injected charge from the nodes 103, 105 and 107, and selectively convey the injected charge to the nodes 101 and 109. For some embodiments, the control voltage C2 may be used to switch the charge injection control elements 201, 203, 205 and 207 between ON and OFF states (e.g., as described below in reference to FIG. 4).

For improved performance, the charge injection control elements 201, 203, 205 and 207 should be designed to have an impedance sufficiently high to prevent degradation of the RF isolation performance of the SOI RF switch 200. However, the charge injection control elements 201, 203, 205 and 207 should also have an impedance sufficiently low to effectively remove the injected charge and avoid degradation of the switching time for the SOI RF switch 200. Further, in some embodiments, the charge injection control elements 201, 203, 205 and 207 are designed so that they do not cause nonlinear behavior and RF harmonic generation. In addition, it is desirable that the charge injection control elements 201, 203, 205 and 207 do not degrade the switching time of the SOI RF switch 200. These design tradeoffs are described in more detail below in reference to FIGS. 3 and 4.

Many configurations of charge injection control elements can be used to remove injected charge from resistively-isolated nodes between switching transistors in SOI RF switches.

SOI RF Switch Circuits with Charge Injection Control Circuits Using Resistors

An embodiment of a charge injection control circuit using resistors to remove injected charge in an SOI RF switch is illustrated in FIG. 3. In FIG. 3, an SOI RF switch 300 includes charge injection control resistors 301, 303, 305 and 307 that comprise elements of a charge injection control circuit. A first node of the charge injection control resistor 301 is operatively connected to the node 101, and a second node of the charge injection control resistor 301 is operatively connected to the node 103. Similarly, a first node of the charge injection control resistor 303 is operatively connected to the node 103, and a second node of the charge injection control resistor 303 is operatively connected to the node 105. Similarly, a first node of the charge injection control resistor 305 is operatively connected to the node 105, and a second node of the charge injection control resistor 305 is operatively connected to the node 107. Similarly, a first node of the charge injection control resistor 307 is operatively connected to the node 107, and a second node of the charge injection control resistor 307 is operatively connected to the node 109. The charge injection control resistors 301, 303, 305 and 307 receive injected charge from the nodes 103, 105 and 107, and convey the injected charge to the nodes 101 and 109.

As noted above, for improved performance, the charge injection control resistors 301, 303, 305 and 307 are designed to have a sufficiently high resistance valve to prevent degradation of the RF isolation performance of the SOI RF switch 300. However, the charge injection control resistors 301, 303, 305 and 307 should also have a low enough resistance to effectively remove the injected charge. Using circuit simulation techniques, good performance has been determined for charge injection resistors selected according to the following equation:
Rc=Rg/N  [EQUATION 1]
In Equation 1, Rc is the resistance of each charge injection control resistor, Rg is the resistance of each gate resistor, and N is the number of RF switching transistors in the stack, also referred to as the “stack height”. It has been determined that choosing the charge injection resistors according to EQUATION 1 provides minimal degradation to the isolation and switching time performance of the SOI RF switch. In one embodiment, SOI RF switch 300 may have gate resistors 121, 123, 125 and 127 that are each 100 K-ohm. In this embodiment, the charge injection control resistors 301, 303, 305 and 307 will each comprise 25 K-ohm resistors, because the stack height N=4 in this example. The present disclosure also encompasses use of charge injection control resistors having Rc values other than as indicated by EQUATION 1. For example, in some embodiments Rc may be selected in the range 10×Rg/N>Rc>Rg/10N.

U.S. application Ser. No. 11/484,370, filed Jul. 10, 2006, pending, incorporated by reference hereinabove, discloses using drain-to-source Rds resistors between the source and drain of a stacked SOI RF switch having an accumulated charge sink. Although the Rds resistors 802, 804, and 806 as shown in FIG. 8, of the U.S. application Ser. No. 11/484,370 have a configuration that is similar to the charge injection control resistors 301, 303, 305 and 307, their function and operation are distinct. In particular, the Rds resistors 802, 804, and 806 are included to allow removal of a DC current generated by using an accumulated charge sink, while the present disclosure provides a solution to the more general problem of charge injection in SOI RF switches that may or may not have an accumulated charge sink.

Charge Injection Control Circuit Using Transistors to Remove Injected Charge

An embodiment of a charge injection control circuit using transistors to remove injected charge in an SOI RF switch is illustrated by FIG. 4.

In FIG. 4 an SOI RF switch 400 includes charge injection control transistors 401, 403, 405 and 407 that comprise elements of a charge injection control circuit. A first and second channel node of the charge injection control transistor 401 are operatively connected to the nodes 101 and 103, respectively. Similarly, a first and second channel node of the charge injection control transistor 403 are operatively connected to the nodes 103 and 105, respectively. Similarly, a first and second channel node of the charge injection control transistor 405 are operatively connected to the nodes 105 and 107, respectively. Similarly, a first and second channel node of the charge injection control transistor 407 are operatively connected to the nodes 107 and 109, respectively.

The gates of the charge injection control transistors 401, 403, 405 and 407 are operatively connected to gate resistors 411, 413, 415 and 417, respectively. The gate resistors 411, 413, 415 and 417 are also connected to a control line 209 to receive a control signal C2 that is conveyed to the gates of the charge injection control transistors 401, 403, 405 and 407. The resistors 411, 413, 415 and 417 are included to enable voltage division of RF signals cross the switching transistors, protect bias circuits, and prevent transmission of parasitic RF signals between the stacked switching transistors.

In one embodiment, in operation, the control signal C2 provides a voltage signal to maintain the charge injection control transistors 401, 403, 405 and 407 in an ON-state during time intervals in which the gate control signal C1 maintains the switching transistors 111, 113, 115 and 117 in an ON-state. For example, the transistors 401, 403, 405, 407, 111, 113, 115 and 117 may all be enhancement-mode n-channel MOSFETs with a threshold voltage of +0.1 V. The gate control signals C1 and C2 may be selected to vary between a voltage of +1.0 V to turn the transistors ON, and a voltage of −3.0 V to turn the transistors OFF.

When the gate control signal C1 transitions from +1 V to −3 V, the voltage passes through the switching transistor threshold voltage +0.1 V. If the gate control signal C2 is maintained at a voltage of +1 V for a time interval after the gate control signal C1 transitions from +1 V to −3 V, the nodes 103, 105 and 107 maintain low resistance connections to the nodes 101 and 109 via the ON-state charge injection control transistors 401, 403, 405 and 407. This low resistance connection conveys the injected charge from the nodes 103, 105 and 107 to the nodes 101 and 109, thereby controlling the charge injection process. After the switching transistors 111, 113, 115 and 117 are in the OFF-state, the charge injection control transistors 401, 403, 405 and 407 may be switched to the OFF-state by changing the gate control signal C2 from +1 V to −3 V.

In order to reduce charge injection via the charge injection control transistors 401, 403, 405 and 407 to the nodes 103, 105 and 107 that may occur when the charge injection control transistors 401, 403, 405 and 407 are switched OFF, the capacitances between the gate nodes and the channel nodes of the charge injection control transistors should be made smaller than the capacitances between the gate nodes and the channel nodes of the switching transistors. This may be accomplished by making the widths of the charge injection control transistors smaller than the widths of the switching transistors. For example, if the charge injection control transistors have a width Wc that is 0.1 times as large as a width Ws of the switching transistors, the charge injection magnitude will be smaller by a factor of approximately 0.1. At this level, the charge injection will be sufficiently small to not degrade performance for an SOI RF switch such the exemplary SOI RF switch 400.

Some advantages of using charge injection control transistors, rather than charge injection control resistors, are reduced switching time and improved switch isolation.

Charge Injection Control Method

In FIG. 5 a charge injection control method 500 is represented by a flow chart diagram. The method begins at a STEP 502, wherein charge injection is caused to occur at resistively isolated nodes of a circuit. In one embodiment, charge injection is generated in an SOI RF switch including stacked switching transistors when the RF switch is switched from an ON-state to an OFF-state. In this embodiment, the charge injection occurs at resistively-isolated nodes located between the switching transistors.

At a STEP 504, the injected charge is conveyed via charge injection control elements from the resistively-isolated nodes to at least one node that is not resistively-isolated. In one embodiment, the charge injection control elements may comprise charge injection control resistors. For this embodiment, the method stops at the STEP 504.

At an optional STEP 506, the charge injection control elements are switched from an ON-state to an OFF-state following a selected time delay interval after the switching transistors are switched from the ON-state to the OFF-state. For example, the STEP 506 is implemented in an embodiment wherein the charge injection control elements comprise charge injection control transistors.

Pulse Method for Controlling Accumulated Charge

As disclosed in U.S. application Ser. No. 11/484,370, filed Jul. 10, 2006, pending, and in U.S. application Ser. No. 11/520,912, filed Sep. 14, 2006, filed Sep. 15, 2005, both incorporated by reference hereinabove, accumulated charge can occur in MOSFET devices that are used in SOI RF switches. A MOSFET device is defined as operating within an “accumulated charge regime” when the MOSFET is biased to operate in an off-state, and when carriers having opposite polarity to the channel carriers are present in the channel region. Accumulated charge in the channel region can degrade the performance of MOSFETs used in SOI RF switches. In particular, the accumulated charge can cause harmonic generation in RF signals and degrade the gate oxide reliability of a MOSFET device.

Accumulated charge in an n-channel MOSFET results from a slow electron-hole pair generation process that occurs when a gate voltage Vg is negative with respect to a source bias voltage Vs and a drain bias voltage Vd. If a positive voltage pulse above a threshold voltage Vth is applied to the gate terminal of the MOSFET, a conducting channel comprising electrons is formed in the body of the MOSFET, and the accumulated charge is dissipated due to drift and recombination. When the gate voltage Vg returns to the negative bias level present prior to the application of the positive voltage pulse, the accumulated charge regenerates in a time period having a time scale that is typically in the millisecond range or longer. Consequently, the accumulated charge in the MOSFET may be controlled by applying a series of positive voltage pulses to the gate terminal. In one example, the pulse rate may be selected by observing harmonic generation in an applied RF signal, and selecting a pulse rate sufficiently high to prevent the harmonic generation from exceeding a desired level.

As a practical effect of applying the pulse method of controlling accumulated charge in an SOI RF switch, charge injection will occur each time the switching transistors are switched from an ON-state to an OFF-state. Consequently, the teachings of the present disclosure for controlling charge injection are also useful when used in conjunction with SOI RF switch systems employing the pulse method for controlling accumulated charge.

Embodiments Using Accumulated Charge Control (ACC) Switching Transistors

Embodiments according to the present teachings may, in some embodiments, use switching transistors (e.g., the switching transistors 111, 113, 115 and 117 of FIGS. 1A, 2, 3 and 4) having an accumulated charge sink (ACS) 610, as shown in FIGS. 6A-6D, and as described in greater detail in U.S. application Ser. No. 11/484,370, filed Jul. 10, 2006, pending, incorporated by reference hereinabove. For example, the switching transistors 111, 113, 115, and 117 (see FIGS. 3-4 and associated description above) may, in some embodiments, comprise accumulated charge control (ACC) transistors described in the above-incorporated application Ser. No. 11/484,370, filed Jul. 10, 2006, and shown in FIGS. 6A-6D. In another embodiment, the switching transistors 111, 113, 115, and 117 may comprise ACC transistors operated according to the pulse method for controlling accumulated charge, as described above and as described in greater detail in the above-incorporated application Ser. No. 11/520,912, filed Sep. 14, 2006.

As shown in FIGS. 6A-6D, in an improved ACC SOI NMOSFET 600, a gate terminal 602 is electrically coupled to a gate 601, a source terminal 604 is electrically coupled to a source 603, and a drain terminal 606 is electrically coupled to a drain 605. Finally, the ACC MOSFET 600 includes an ACS terminal 608 that is electrically coupled to the ACS 610.

The ACC SOI NMOSFET 600 may be operated using various techniques and implemented in various circuits in order to control accumulated charge present in the FET when it is operating in an accumulated charge regime. For example, in one exemplary embodiment as shown in FIG. 6B, the gate and ACS terminals, 602 and 608, respectively, are electrically coupled together. In one embodiment of the simplified circuit shown in FIG. 6B, the source and drain bias voltages applied to the terminals 604 and 606, respectively, may be zero. If the gate bias voltage (Vg) applied to the gate terminal 602 is sufficiently negative with respect to the source and drain bias voltages (Vs and Vd, respectively) applied to the terminals 604 and 606, and with respect to the threshold voltage Vth, (for example, if Vth is approximately zero, and if Vg is more negative than approximately −1 V) the ACC NMOSFET 600 operates in the accumulated charge regime. When the MOSFET operates in this regime, accumulated charge (holes) may accumulate in the NMOSFET 600.

Advantageously, the accumulated charge can be removed via the ACS terminal 608 by connecting the ACS terminal 608 to the gate terminal 602 as shown in FIG. 6B. This configuration ensures that when the FET 600 is operated in the OFF-state, it is held in the correct bias region to effectively remove or otherwise control the accumulated charge. As shown in FIG. 6B, connecting the ACS terminal 608 to the gate ensures that the same bias voltages are applied to both the gate (Vg) and the ACS 610 (VACS). The accumulated charge is thereby removed from the SOI NMOSFET 600 via the ACS terminal 608.

In other exemplary embodiments, as described with reference to FIG. 6C, for example, Vs and Vd may comprise nonzero bias voltages. According to these examples, Vg must be sufficiently negative to both Vs and Vd in order for Vg to be sufficiently negative to Vth to turn the NMOSFET 600 OFF (i.e., operate the NMOSFET 600 in the OFF-state). When so biased, as described above, the NMOSFET 600 may enter the accumulated charge regime. For this example, the voltage VACS may also be selected to be equal to Vg by connecting the ACS terminal 608 to the gate terminal 602, thereby conveying the accumulated charge from the ACC NMOSFET, as described above.

Another exemplary simplified circuit using the improved ACC SOI NMOSFET 600 is shown in FIG. 6C. As shown in FIG. 6C, in this embodiment, the ACS terminal 608 may be electrically coupled to a diode 610, and the diode 610 may, in turn, be coupled to the gate terminal 602. This embodiment may be used to prevent a positive current flow into the ACS 610 caused by a positive Vg-to-Vs (or, equivalently, Vgs, where Vgs=Vg−Vs) bias voltage, as may occur, for example, when the SOI NMOSFET 300 is biased into an ON-state condition.

As with the device shown in FIG. 6B, when biased OFF, the ACS terminal 608 voltage VACS comprises the gate voltage plus a voltage drop across the diode 610. At very low ACS terminal 610 current levels, the voltage drop across the diode 610 typically also is very low (e.g., <<500 mV, for example, for a typical threshold diode).

When the SOI NMOSFET 600 is biased in an ON-state condition, the diode 610 is reverse-biased, thereby preventing the flow of positive current into the source and drain regions. The reverse-biased configuration reduces power consumption and improves linearity of the device. The circuit shown in FIG. 6C therefore works well to remove the accumulated charge when the FET is in the OFF-state and is operated in the accumulated charge regime. It also permits almost any positive voltage to be applied to the gate voltage Vg. This, in turn, allows the ACC MOSFET to effectively remove accumulated charge when the device operates in the OFF-state, yet assume the characteristics of a floating body device when the device operates in the ON-state.

With the exception of the diode 610 used to prevent the flow of positive current into the ACS terminal 608, exemplary operation of the simplified circuit shown in FIG. 6C is the same as the operation of the circuit described above with reference to FIG. 6B.

In yet another embodiment, the ACS terminal 608 may be coupled to a control circuit 612 as illustrated in the simplified circuit of FIG. 6D. The control circuit 612 may provide a selectable ACS bias voltage VACS that selectively controls the accumulated charge.

Method of Fabrication

With varying performance results, RF switches have heretofore been implemented in different component technologies, including bulk complementary-metal-oxide-semiconductor (CMOS) and gallium-arsenide (GaAs) technologies. In fact, most high-performance high-frequency switches use GaAs technology.

Although GaAs RF switch implementations offer improved performance characteristics relative to bulk CMOS, the technology has several disadvantages. For example, GaAs technology exhibits relatively low yields of properly functioning integrated circuits. GaAs RF switches tend to be relatively expensive to design and manufacture. In addition, although GaAs switches exhibit improved insertion loss characteristics as described above, they may have low frequency limitations due to slow states present in the GaAs substrate. The technology also does not lend itself to high levels of integration, which requires that digital control circuitry associated with the RF switch be implemented “off chip” from the switch. The low power control circuitry associated with the switch has proven difficult to integrate. This is disadvantageous as it both increases the overall system cost or manufacture, size and complexity, as well as reducing system throughput speeds.

In one embodiment of the present disclosure, the exemplary circuits described hereinabove are implemented using a fully insulating substrate silicon-on-insulator (SOI) technology. More specifically, the MOSFET transistors of the present disclosure are implemented using “Ultra-Thin-Silicon (UTSi)” (also referred to herein as “ultrathin silicon-on-sapphire”) technology. In accordance with UTSi manufacturing methods, the transistors used to implement the inventive RF switch are formed in an extremely thin layer of silicon in an insulating sapphire wafer. The fully insulating sapphire substrate enhances the performance characteristics of the inventive RF switch by reducing the deleterious substrate coupling effects associated with non-insulating and partially insulating substrates. For example, improvements in insertion loss are realized by lowering the transistor ON-state resistances and by reducing parasitic substrate conductances and capacitances. In addition, switch isolation is improved using the fully insulating substrates provided by UTSi technology. Owing to the fully insulating nature of silicon-on-sapphire technology, the parasitic capacitance between the nodes of the RF switches are greatly reduced as compared with bulk CMOS and other traditional integrated circuit manufacturing technologies.

Silicon on Insulator RF Integrated Circuits

As is well known, SOI has been used in the implementation of high performance microelectronic devices, primarily in applications requiring radiation hardness and high speed operation. SOI technologies include, for example, SIMOX, bonded wafers having a thin silicon layer bonded to an insulating layer, and silicon-on-sapphire. In order to achieve the desired RF switch performance characteristics described hereinabove, in one embodiment, the inventive RF switch is fabricated on a sapphire substrate.

Fabrication of devices on an insulating substrate requires that an effective method for forming silicon CMOS devices on the insulating substrate be used. The advantages of using a composite substrate comprising a monocrystalline semiconductor layer, such as silicon, epitaxially deposited on a supporting insulating substrate, such as sapphire, are well-recognized, and can be realized by employing as the substrate an insulating material, such as sapphire (Al2O3), spinel, or other known highly insulating materials, and providing that the conduction path of any inter-device leakage current must pass through the substrate.

An “ideal” SOI wafer can be defined to include a completely monocrystalline, defect-free silicon layer of sufficient thickness to accommodate the fabrication of active devices therein. The silicon layer would be adjacent to an insulating substrate and would have a minimum of crystal lattice discontinuities at the silicon-insulator interface. Early attempts to fabricate this “ideal” silicon-on-insulator wafer were frustrated by a number of significant problems, which can be summarized as (1) substantial incursion of contaminants into the epitaxially deposited silicon layer, especially the p-dopant aluminum, as a consequence of the high temperatures used in the initial epitaxial silicon deposition and the subsequent annealing of the silicon layer to reduce defects therein; and (2) poor crystalline quality of the epitaxial silicon layers when the problematic high temperatures were avoided or worked around through various implanting, annealing, and/or re-growth schemes.

It has been found that the high quality silicon films suitable for demanding device applications can be fabricated on sapphire substrates by a method that involves epitaxial deposition of a silicon layer on a sapphire substrate, low temperature ion implant to form a buried amorphous region in the silicon layer, and annealing the composite at temperatures below about 950 degrees C.

Examples of and methods for making such silicon-on-sapphire devices are described in U.S. Pat. No. 5,416,043 (“Minimum charge FET fabricated on an ultrathin silicon on sapphire wafer”); U.S. Pat. No. 5,492,857 (“High-frequency wireless communication system on a single ultrathin silicon on sapphire chip”); U.S. Pat. No. 5,572,040 (“High-frequency wireless communication system on a single ultrathin silicon on sapphire chip”); U.S. Pat. No. 5,596,205 (“High-frequency wireless communication system on a single ultrathin silicon on sapphire chip”); U.S. Pat. No. 5,600,169 (“Minimum charge FET fabricated on an ultrathin silicon on sapphire wafer”); U.S. Pat. No. 5,663,570 (“High-frequency wireless communication system on a single ultrathin silicon on sapphire chip”); U.S. Pat. No. 5,861,336 (“High-frequency wireless communication system on a single ultrathin silicon on sapphire chip”); U.S. Pat. No. 5,863,823 (“Self-aligned edge control in silicon on insulator”); U.S. Pat. No. 5,883,396 (“High-frequency wireless communication system on a single ultrathin silicon on sapphire chip”); U.S. Pat. No. 5,895,957 (“Minimum charge FET fabricated on an ultrathin silicon on sapphire wafer”); U.S. Pat. No. 5,920,233 (“Phase locked loop including a sampling circuit for reducing spurious side bands”); U.S. Pat. No. 5,930,638 (“Method of making a low parasitic resistor on ultrathin silicon on insulator”); U.S. Pat. No. 5,973,363 (“CMOS circuitry with shortened P-channel length on ultrathin silicon on insulator”); U.S. Pat. No. 5,973,382 (“Capacitor on ultrathin semiconductor on insulator”); and U.S. Pat. No. 6,057,555 (“High-frequency wireless communication system on a single ultrathin silicon on sapphire chip”). All of these referenced patents are incorporated herein in their entirety for their teachings on ultrathin silicon-on-sapphire integrated circuit design and fabrication.

Using the methods described in the patents referenced above, electronic devices can be formed in an extremely thin layer of silicon on an insulating synthetic sapphire wafer. The thickness of the silicon layer is typically less than 150 nm. Such an “ultrathin” silicon layer maximizes the advantages of the insulating sapphire substrate and allows the integration of multiple functions on a single integrated circuit. Traditional transistor isolation wells required for thick silicon are unnecessary, simplifying transistor processing and increasing circuit density. To distinguish these above-referenced methods and devices from earlier thick-silicon embodiments, they are herein referred to collectively as “ultrathin silicon-on-sapphire.”

In some embodiments of the present disclosure, the MOS transistors may be formed in ultrathin silicon-on-sapphire wafers by the methods disclosed in U.S. Pat. Nos. 5,416,043; 5,492,857; 5,572,040; 5,596,205; 5,600,169; 5,663,570; 5,861,336; 5,863,823; 5,883,396; 5,895,957; 5,920,233; 5,930,638; 5,973,363; 5,973,382; and 6,057,555. However, other known methods of fabricating silicon-on-sapphire integrated circuits can be used without departing from the spirit or scope of the present teachings.

A number of embodiments of the present inventive concept have been described. Nevertheless, it will be understood that various modifications may be made without departing from the scope of the inventive teachings. For example, it should be understood that many types of switch circuits (e.g., single-pole single-throw, single-pole double-throw, double-throw-pole double-throw, etc.) may be used according to the present teachings. In another example, it should be noted that although embodiments having SOI RF switches have been used herein for exemplary purposes, persons skilled in the electronic arts will understand that the present teachings may be applied to many other types of switching circuits having isolated nodes wherein charge injection may occur.

Accordingly, it is to be understood that the inventive concept is not to be limited by the specific illustrated embodiments, but only by the scope of the appended claims. The description may provide examples of similar features as are recited in the claims, but it should not be assumed that such similar features are identical to those in the claims unless such identity is essential to comprehend the scope of the claim. In some instances the intended distinction between claim features and description features is underscored by using slightly different terminology.

Claims

1. A switch circuit, comprising:

a plurality of switching transistors coupled in series to selectively convey a signal from an input of the series coupled switching transistors to an output of the series coupled switching transistors; the series of switching transistors including:
a plurality of resistively-isolated nodes, each resistively-isolated node located between a different pair of the switching transistors in series; and
at least one non-resistively-isolated node located adjacent to one of the plurality of the switching transistors in series; and
a plurality of charge injection control modules, each control module operatively coupled to a different one of the plurality of resistively-isolated nodes and the at least one non-resistively-isolated node to communicate injected charge from the different one of plurality of resistively-isolated nodes to the at least one non-resistively-isolated node.

2. The switch circuit of claim 1, wherein each of the switching transistors has an associated and corresponding charge injection control module, the switching transistor drain node coupled to its associated and corresponding charge injection control-module first node and the switching transistor source node coupled to its associated and corresponding charge injection control module second node, and the charge injection control module communicates injected charge between the switching transistor drain node and source node.

3. The switch circuit of claim 1, wherein each of the switching transistors has an associated and corresponding charge injection control module, the different one of the plurality of resistively-isolated nodes is operatively coupled to the switching transistor drain node and the at least one non-resistively-isolated node is operatively coupled to the switching transistor source node.

4. The switch circuit of claim 3, wherein each switching transistor includes an accumulated charge sink (ACS) electrically coupled to convey accumulated charge from the ACS to a gate node of the transistor when the transistor operates in an accumulated charge regime.

5. The switch circuit of claim 4, wherein the switching transistor including a diode, the diode selectively conveying accumulated charge from the ACS to the transistor gate node when the transistor operates in an accumulated charge regime.

6. The switch circuit of claim 2, wherein each charge injection control element comprises a charge injection control resistor.

7. The switch circuit of claim 6, further comprising a plurality of gate resistors each having a resistance Rg, wherein a gate of each switching transistor is connected to an associated and corresponding one of the plurality of gate resistors, and wherein the plurality of gate resistors is connected to a control line that conveys a control signal to the gate of each switching transistor, and wherein a resistance Rc of each charge injection control resistor is selected according to a formula 10×RgN>Rc>Rg/10N, and wherein N comprises a number of switching transistors in the plurality of switching transistors.

8. The switch circuit of claim 2, wherein each charge injection control module includes a switch module having an ON-state and an OFF-state, and wherein a control signal selectively switches the charge injection control modules switch module from the ON-state to the OFF-state to control the communication of injection charge.

9. The switch circuit of claim 8, wherein the series of switch transistors are switched to an ON-state during a first time interval, and the charge injection control modules switch modules are switched to an ON-state during a second time interval at least partially subsequent to the first time interval.

10. The switch circuit of claim 1, wherein the switch circuit includes a radio frequency (RF) switch.

11. The switch circuit of claim 4, wherein the series of switching transistors are operated using a pulse method to control accumulated charge.

12. The switch circuit of claim 1, wherein each of the plurality of switching transistors includes a semiconductor-on-insulator (SOI) metal-oxide-semiconductor field effect transistor (MOSFET).

13. The switch circuit of claim 12, wherein the SOI MOSFETs include a silicon-on-sapphire substrate.

14. A method of controlling charge injection in a switch circuit, including:

employing a plurality of switching transistors coupled in series to selectively convey a signal from an input of the series coupled switching transistors to an output of the series coupled switching transistors; the series of switching transistors including: a plurality of resistively-isolated nodes, each resistively-isolated node located between a different pair of the switching transistors in series; and at least one non-resistively-isolated node located adjacent to one of the plurality of the switching transistors in series;
generating injected charge at the plurality of resistively-isolated nodes; and
operatively coupling one of a plurality of charge injection control modules to a different one of the plurality of resistively-isolated nodes and the at least one non-resistively-isolated node to communicate injected charge from the different one of plurality of resistively-isolated nodes to the at least one non-resistively-isolated node.

15. The method of claim 14, wherein each of the switching transistors has an associated and corresponding charge injection control module, coupling the switching transistor drain node to its associated and corresponding charge injection control-module first node and coupling the switching transistor source node to its associated and corresponding charge injection control module second node, and employing the charge injection control module to communicate injected charge between the switching transistor drain node and source node.

16. The method of claim 14, wherein each of the switching transistors has an associated and corresponding charge injection control module, operatively coupling the different one of the plurality of resistively-isolated nodes to the switching transistor drain node, and operatively coupling the at least one non-resistively-isolated node to the switching transistor source node.

17. The method of claim 16, wherein each switching transistor includes an accumulated charge sink (ACS) electrically coupled to a gate node of the transistor and communicating accumulated charge from the ACS to a gate node of the transistor when the transistor operates in an accumulated charge regime.

18. The method of claim 17, wherein the switching transistor including a diode, employing the diode to selectively communicate accumulated charge from the ACS to the transistor gate node when the transistor operates in an accumulated charge regime.

19. The method of claim 15, wherein each charge injection control element comprises a charge injection control resistor.

20. The method of claim 15, wherein each charge injection control module includes a switch module having an ON-state and an OFF-state, and selectively switching the charge injection control modules switch module from the ON-state to the OFF-state to control the communication of injection charge.

21. The method of claim 20, further including switching the series of switch transistors to an ON-state during a first time interval, and switching the charge injection control module switch modules to an ON-state during a second time interval at least partially subsequent to the first time interval.

22. The method of claim 14, wherein the switch circuit includes a radio frequency (RF) switch.

23. The method of claim 17, further including operating the series of switching transistors using a pulse method to control accumulated charge.

24. A switch circuit, including:

a plurality of switching transistors coupled in series to selectively convey a signal from an input of the series coupled switching transistors to an output of the series coupled switching transistors; the series of switching transistors including: a plurality of resistively-isolated nodes, each resistively-isolated node located between a different pair of the switching transistors in series; and at least one non-resistively-isolated node located adjacent to one of the plurality of the switching transistors in series;
a) means for generating injected charge at the plurality of resistively-isolated nodes; and
b) means, operatively coupled to the generating means, for communicating injected charge from the different one of plurality of resistively-isolated nodes to the at least one non-resistively-isolated node.

25. The switch circuit of claim 24, wherein the communicating means comprises a plurality of charge injection control modules, and wherein each of the switching transistors has an associated and corresponding charge injection control module, and the switching transistor drain node-coupled to its associated and corresponding charge injection control-module first node and the switching transistor source node coupled to its associated and corresponding charge injection control module second node, and the charge injection control module communicates injected charge between the switching transistor drain node and source node.

26. The switch circuit of claim 24, wherein each of the switching transistors has an associated and corresponding charge injection control module, the different one of the plurality of resistively-isolated nodes is operatively coupled to the switching transistor drain node and the at least one non-resistively-isolated node is operatively coupled to the switching transistor source node.

27. The switch circuit of claim 25, wherein each charge injection control element comprises a charge injection control resistor.

28. The switch circuit of claim 27, further comprising a plurality of gate resistors each having a resistance Rg, wherein a gate of each switching transistor is connected to an associated and corresponding one of the plurality of gate resistors, and wherein the plurality of gate resistors is connected to a control line that conveys a control signal to the gate of each switching transistor, and wherein a resistance Rc of each charge injection control resistor is selected according to a formula 10×Rg/N>Rc>Rg/10N, and wherein N comprises a number of switching transistors in the plurality of switching transistors.

29. The switch circuit of claim 25, wherein each charge injection control module includes a switch module having an ON-state and an OFF-state, and wherein a control signal selectively switches the charge injection control modules switch module from the ON-state to the OFF-state to control the communication of injection charge.

30. The switch circuit of claim 29, wherein the series of switch transistors are switched to an ON-state during a first time interval, and the charge injection control modules switch modules are switched to an ON-state during a second time interval at least partially subsequent to the first time interval.

31. The switch circuit of claim 8, wherein each charge injection control module further includes a control resistor.

32. The switch circuit of claim 31, further comprising a plurality of gate resistors each having a resistance Rg, wherein a gate node of each switching transistor is connected to an associated and corresponding one of the plurality of gate resistors, and wherein the plurality of gate resistors is connected to a control line that conveys a control signal to the gate of each switching transistor, and wherein a resistance Rc of each control resistor is selected according to a formula 10×Rg/N>Rc>Rg/10N, and wherein N comprises the number of switching transistors in the plurality of switching transistors.

33. The switch circuit of claim 20, further employing a control resister in each charge injection control module.

34. The switch circuit of claim 29, wherein each charge injection control module further includes a control resistor.

35. The switch circuit of claim 34, further comprising a plurality of gate resistors each having a resistance Rg, wherein a gate node of each switching transistor is connected to an associated and corresponding one of the plurality of gate resistors, and wherein the plurality of gate resistors is connected to a control line that conveys a control signal to the gate of each switching transistor, and wherein a resistance Rc of each control resistor is selected according to a formula 10×Rg/N>Rc>Rg/10N, and wherein N comprises the number of switching transistors in the plurality of switching transistors.

Referenced Cited
U.S. Patent Documents
3699359 October 1972 Shelby
4053916 October 11, 1977 Cricchi et al.
5012123 April 30, 1991 Ayasli et al.
5313083 May 17, 1994 Schindler
5416043 May 16, 1995 Burgener et al.
5492857 February 20, 1996 Reedy et al.
5548239 August 20, 1996 Kohama
5553295 September 3, 1996 Pantelakis et al.
5572040 November 5, 1996 Reedy et al.
5596205 January 21, 1997 Reedy et al.
5600169 February 4, 1997 Burgener et al.
5663570 September 2, 1997 Reedy et al.
5777530 July 7, 1998 Nakatuka
5801577 September 1, 1998 Tailliet
5818099 October 6, 1998 Burghartz
5861336 January 19, 1999 Reedy et al.
5863823 January 26, 1999 Burgener
5883396 March 16, 1999 Reedy et al.
5895957 April 20, 1999 Reedy et al.
5920233 July 6, 1999 Denny
5930638 July 27, 1999 Reedy et al.
5945867 August 31, 1999 Uda et al.
5973363 October 26, 1999 Staab et al.
5973382 October 26, 1999 Burgener et al.
6057555 May 2, 2000 Reedy et al.
6066993 May 23, 2000 Yamamoto et al.
6249027 June 19, 2001 Burr
6452232 September 17, 2002 Adan
6504212 January 7, 2003 Allen et al.
6631505 October 7, 2003 Arai
6632724 October 14, 2003 Henley et al.
6642578 November 4, 2003 Arnold et al.
6693326 February 17, 2004 Adan
6790747 September 14, 2004 Henley et al.
6804502 October 12, 2004 Burgener et al.
6898778 May 24, 2005 Kawanaka
6908832 June 21, 2005 Farrens et al.
6969668 November 29, 2005 Kang et al.
6978437 December 20, 2005 Rittman et al.
7056808 June 6, 2006 Henley et al.
7058922 June 6, 2006 Kawanaka
7404157 July 22, 2008 Tanabe
20010015461 August 23, 2001 Ebina
20030205760 November 6, 2003 Kawanaka et al.
Foreign Patent Documents
1256521 June 2000 CN
0788185 August 1997 EP
1 006 584 June 2000 EP
2387094 November 2011 EP
A-06-334506 December 1994 JP
A-08-307305 November 1996 JP
A-10-242829 September 1998 JP
10-344247 December 1998 JP
Other references
  • Stuber, Response filed in USPTO dated Jan. 20, 2009 for related U.S. Appl. No. 11/484,370, 5 pgs.
  • Stuber, Michael, et al., Amendment filed in USPTO dated Mar. 16, 2009 for related U.S. Appl. No. 11/520,912, 22 pgs.
  • Nguyen, Tram Hoang, Office Action received from USPTO dated Apr. 23, 2009 for related U.S. Appl. No. 11/484,370, 11 pgs.
  • Ebner Von Eschenbach, Jennifer, Communication from the EPO dated Feb. 4, 2009 for related appln No. 06786943.8, 7 pgs.
  • Hoffmann, Niels, International Search Report from the EPO dated Nov. 7, 2006 for related appln. No. PCT/US2006/026965, 19 pgs.
  • Tat, Binh C., Office Action received from USPTO dated Jul. 8, 2009 for related U.S. Appl. No. 11/520,912, 6 pgs.
  • Photocopy of a translation of an Office Action dated Jul. 31, 2009 for related Chinese appln. No. 200680025128.7, 3 pages.
  • Brindle, et al, Response filed in the USPTO dated Aug. 24, 2009 for related U.S. Appl. No. 11/484,370, 5 pages.
  • Tat, Binh C., International Search Report and Written Opinion dated Jul. 3, 2008 for related PCT application No. PCT/US06/36240, 7 pgs.
  • Tat, Binh C., Office Action received from USPTO dated Sep. 15, 2008 for related U.S. Appl. No. 11/520,912, 18 pgs.
  • Nguyen, Tram Hoang, Office Action received from USPTO dated Sep. 19, 2008 for related U.S. Appl. No. 11/484,370, 7 pages.
  • Tat, Binh C., Office Action received from USPTO dated Dec. 10, 2009 for related U.S. Appl. No. 11/520,912, 19 pages.
  • Nguyen, Tram Hoang, an Office Action received from the USPTO for related U.S. Appl. No. 11/484,370, dated Jan. 6, 2010, 46 pgs.
  • Brindle, Chris, et al., Translation of a Response filed in the Chinese Patent Office for related appln No. 200680025128.7 dated Nov. 30, 2009, 3 pages.
  • Weman, Eva, Communication under Rule 71(3) EPC received from the EPO for related appln. No. 02800982.7-220 dated Nov. 27, 2010, 60 pages.
  • Morena, Enrico, Supplementary European Search Report for related appln. No. 06814836.0 dated Feb. 17, 2010, 8 pages.
  • Kuang, J.B., et al., “A Floating-Body Charge Monitoring Technique for Partially Depleted SOI Technology”, Int. J. of Electonics, vol. 91, No. 11, Nov. 11, 2004, pp. 625-637.
  • Brindle, Chris, et al., Translation of a Response filed in the Chinese Patent Office for related appln No. 200680025128.7. dated Nov. 30, 2009, 3 pages.
  • Kelly, Dylan, et al., Response and Terminal Disclaimers filed in the USPTO for related U.S. Appl. No. 11/347,014, dated Mar. 16, 2010, 5 pages.
  • Tieu, Binh Kien, Notice of Allowance received from the USPTO for related U.S. Appl. No. 11/347,014, dated Apr. 29, 2010, 12 pages.
  • Chow, Charles Chiang, Notice of Allowance received from the USPTO dated Aug. 16, 2011 for related U.S. Appl. No. 11/347,671, 12 pgs.
  • Hoffmann, N, Summons to attend oral proceedings pursuant to Rule 115(1) EPC received from the EPO dated Jul. 22, 2011 for related appln. No. 06786943.8, 8 pgs.
  • Nguyen, Tram Hoang, Notice of Allowance received from the USPTO for related U.S. Appl. No. 11/484,370 dated Nov. 12, 2010, 21 pgs.
  • Shifrin, Mitchell B., “Monolithic FET Structures for High-Power Control Component Applications”, IEEE Transactions on Microwave Theory and Techniques, vol. 37, No. 12, Dec. 1989, pp. 2134-2141.
  • Stuber, Michael, et al., Photocopy of a Response that was filed in the UPSTO for related U.S. Appl. No. 11/520,060, dated Sep. 8, 2009, 3 pgs.
  • F. Hameau and O. Rozeau, “Radio-Frequency Circuits Integration Using CMOS SOI 0.25um Technology”, 2002 RF IC Design Workshop Europe, Mar. 19-22, 2002, Grenoble, France.
  • O. Rozeau, et al., “SOI Technologies Overview for Low-Power Low-Voltage Radio-Frequency Applications,” Analog Integrated Circuits and Signal Processing, 25, pp. 93-114, Boston, MA, Kluwer Academic Publishers, Nov. 2000.
  • C. Tinella, et al., “A High-Performance CMOS-SOI Antenna Switch for the 2.5 5-GHz Band,” IEEE Journal of Solid-State Circuits, vol. 38, No. 7, Jul. 2003.
  • H. Lee, et al., “Analysis of body bias effect with PD-SOI for analog and RF applications,” Solid Sate Electron, vol. 46, pp. 1169-1176, 2002.
  • J. H. Lee, et al., “Effect of Body Structure on Analog Performance of SOI NMOSFETs”, Proceedings, 1998 IEEE International SOI Conference, Oct. 5-8, 1998, pp. 61-62.
  • C.F. Edwards, et al., “The Effect of Body Contact Series Resistance on SOI CMOS Amplifier Stages”, IEEE Transactions on Electron Devices, vol. 44, No. 12, Dec. 1997, pp. 2290-2294.
  • S. Maeda, et al., “Substrate-bias Effect and Source-drain Breakdown Characteristics in Body-tied Short-channel SOI MOSFETs”, IEEE Transactions on Electron Devices, vol. 46, No. 1, Jan. 1999, pp. 151-158.
  • F. Assaderaghi, et al., “Dynamic Threshold-voltage MOSFET (DTMOS) for Ultra-low Voltage VLSI”, IEEE Transactions on Electron Devices, vol. 44, No. 3, Mar. 1997, pp. 414-422.
  • G. O. Workman and J. G. Fossum, “A Comparative Analysis of the Dynamic Behavior of BTG/SOI MOSFETs and Circuits with Distributed Body Resistance”, IEEE Transactions on Electron Devices, vol. 45, No. 10, Oct. 1998, pp. 2138-2145.
  • T. Sh. Chao, et al., “High-voltage and High-temeratuve Applications of DTMOS with Reverse Schottky Barrier on Substrate Contacts”, IEEE Electron Device Letters, vol. 25, No. 2, Feb. 2004, pp. 86-88.
  • Wei, et al., “Measurement of Transient Effects in SOI DRAM/SRAM Access Transistors”, IEEE Electron Device Letters, vol. 17, No. 5, May 1996.
  • Kuang, et al., “SRAM Bitline Circuits on PD SOI: Advantages and Concerns”, IEEE Journal of Solid-State Circuits, vol. 32, No. 6, Jun. 1997.
  • Sleight, et al., “Transient Measurements of SOI Body Contact Effectiveness”, IEEE Electron Device Letters, vol. 19, No. 12, Dec. 1998.
  • Chung, et al., “SOI MOSFET Structure with a Junction-Type Body Contact for Suppression of Pass Gate Leakage”, IEEE Transactions on Electron Devices, vol. 48, No. 7, Jul. 2001.
  • Lee, et al., “Effects of Gate Structures on the RF Performance in PD SOI MOSFETs”, IEEE Microwave and Wireless Components Letters, vol. 15, No. 4, Apr. 2005.
  • Hirano, et al., “Impact of Actively Body-bias Controlled (ABC) SOI SRAM by using Direct Body Contact Technology for Low-Voltage Application”, IEEE, 2003, pp. 2.4.1-2.4.4.
  • Lee, et al., “Harmonic Distortion Due to Narrow Width Effects in Deep sub-micron SOI-CMOS Device for analog-RF applications”, 2002 IEEE International SOI Conference, Oct. 2002.
  • Orndorff, et al., “CMOS/SOS/LSI Switching Regulator Control Device”, ISSCC 78, Feb. 17, 1978, IEEE International Solid-State Circuits Conference, pp. 234-235 and 282.
  • Suehle, et al., “Low Electric Field Breakdown of Thin Si02 Films Under Static and Dynamic Stress”, IEEE Transactions on Electron Devices, vol. 44, No. 5, May 1997.
  • Bolam, et al., “Reliability Issues for Silicon-on-Insulator”, IMB Microelectronics Division, IEEE 2000, pp. 6.4.1-6.4.4.
  • Hu, et al., “A Unified Gate Oxide Reliability Model”, IEEE 37th Annual International Reliability Physics Symposium, San Diego, CA 1999, pp. 47-51.
  • Kuo, et al., “Low-Voltage SOI CMOS VLSI Devices and Circuits”, 2001, Wiley Interscience, New York, P001090589, pp. 57-60 and 349-354.
  • Johnson, et al., “Advanced Thin-Film Silicon-on-Sapphire Technology: Microwave Circuit Applications”, IEEE Transactions on Electron Devices, vol. 45, No. 5, May 1998, pp. 1047-1054.
  • Miyajima, Notice of Reasons for Refusal received from the Japanese Patent Office for appln. No. 2003-535287 dated Feb. 13, 2006, 3 pgs.
  • Tieu, Binh, Office Action received from USPTO dated Jan. 17, 2006 for U.S. Appl. No. 10/922,135, 8 pgs.
  • Burgener, Response filed in the UPSTO including Terminal Disclaimer dated May 16, 2006 for U.S. Appl. No. 10/922,135, 3 pgs.
  • Tieu, Binh, Notice of Allowance received from the USPTO dated Jun. 2, 2006 for U.S. Appl. No. 10/922,135, 5 pgs.
  • Tieu, Binh, Notice of Allowance received from the USPTO dated May 12, 2004 for U.S. Appl. No. 10/267,531, 7 pgs.
  • Burgener, et al., Comments on Examiner's Statement of Reasons for Allowance dated Aug. 12, 2004 for U.S. Appl. No. 10/267,531, 2 pgs.
  • Unterberger, Michael, Extended Search Report received from the EPO dated Sep. 30, 2011 for related appln. No. 10011669.8, 9 pgs.
  • Translation of Chinese Office Action received from the CPA dated Nov. 2, 2011 for related appln. No. 2006-80025128.7, 12 pgs.
  • Weman, Eva, Communication of a Notice of Opposition received from the EPO dated Nov. 8, 2011 for related appln. No. 028000982.7, 34 pgs.
  • Voye-Piccoli, Notice of European Publication received from the EPO dated Oct. 19, 2011 for related appln. No. 10011669.8, 1 pg.
  • Nguyen, Tram Hoang, Notice of Allowance received from the USPTO dated Nov. 17, 2011 for related U.S. Appl. No. 13/053,211, 41 pgs.
Patent History
Patent number: 8143935
Type: Grant
Filed: Jul 26, 2007
Date of Patent: Mar 27, 2012
Patent Publication Number: 20080076371
Assignee: Peregrine Semiconductor Corporation (San Diego, CA)
Inventors: Alexander Dribinsky (Naperville, IL), Tae Youn Kim (San Diego, CA), Dylan J. Kelly (San Diego, CA), Christopher N. Brindle (Poway, CA)
Primary Examiner: Michael Shingleton
Attorney: Jaquez & Associates
Application Number: 11/881,816
Classifications
Current U.S. Class: Field-effect Transistor (327/427); Plural Sections Connected In Parallel (e.g., Power Mosfet) (257/341); Subscriber Equipment (455/425)
International Classification: H03K 17/00 (20060101);