Abstract: A conductive blank enables election beam (e-beam) patterning rather than optical patterning for the phase level etch of a phase-shifting mask (PSM) photomask. The conductive blank includes a conductive layer between a chrome (pattern) layer and a quartz substrate. The chrome layer is patterned with in-phase and phased features, and then is recoated with a resist layer. An e-beam exposure tool exposes the resist layer over the phased features. The still intact conductive layer under the chrome layer dissipates any charge buildup in the resist layer during this process. A phase level etch then etches through the conductive layer and creates a pocket in the quartz. A subsequent isotropic etch through both the in-phase and phased features removes the conductive layer at the in-phase features and improves exposure radiation transmission intensity. Alternatively, a visually transparent conductive layer can be used, eliminating the need to etch through the in-phase features.

Abstract: In a computer implemented synthesis system, a method of generating a test pattern for use in testing device with ATE (automated test equipment). The computer implemented steps of receiving a netlist specification representing a design to be realized in physical form and storing the netlist specification in a computer memory unit, and simulating the netlist using the computer implemented synthesis system. Using the simulation instantiated within the synthesis system, deterministic test pattern generation is performed to obtain a first portion (partial) of a test pattern. The test pattern is operable to detect a fault in the circuit netlist once speculative test pattern generation is performed to obtain a remaining portion of the test pattern. The first portion and the remaining portion of the test pattern comprise a test vector operable to detect the fault when used with automated test equipment for testing a device resulting from the design.

Abstract: Techniques for fabricating a device include forming a fabrication layout, such as a mask layout, for a physical design layer, such as a design for an integrated circuit, and identifying evaluation points on an edge of a polygon corresponding to the design layer for correcting proximity effects. Techniques include correcting for proximity effects associated with an edge in a first fabrication layout by determining whether any portion of the edge corresponds to a target edge in a design layer. The first fabrication layout corresponds to the design layer that indicates target edges for a printed features layer. If any portion of the edge corresponds to the target edge, then it is determined whether to establish an evaluation point on the edge. Then it is determined how to correct the edge for proximity effects based on the evaluation point. In case it is determined that no portion of the edge corresponds to the target edge, then no evaluation point is selected on the edge.

Abstract: Techniques for forming a design layout with phase-shifted features, such as an integrated circuit layout, include receiving information about a particular phase-shift conflict in a first physical design layout. The information indicates one or more features logically associated with the particular phase-shift conflict. Then the first physical design layout is adjusted based on that information to produce a second design layout. The adjustments rearrange features in a unit of the design layout to collect free space around a selected feature associated with the phase-shift conflict. With these techniques, a unit needing more space for additional shifters can obtain the needed space during the physical design process making the adjustment. The needed space so obtained allows the fabrication design process to avoid or resolve phase conflicts while forming a fabrication layout, such as a mask, for substantiating the design layout in a printed features layer, such as in an actual integrated circuit.

Abstract: According to the present invention, during scan conversion, non-scan memory cells of a circuit design are replaced with scan cells to form a scan chain. The scan chain is transformed by the test synthesis tool of the present invention into dynamic scan chains with the addition of reconfiguration circuitry. The reconfiguration circuitry partitions the scan chain into multiple segments and enables each segment to be selectively “bypassed” (or deactivated) during test application. Shorter test patterns that are only pertinent to one or more segments are necessary, resulting in a reduction in overall test data volume and test application time. The present invention also provides a modified ATPG technique for generating test patterns for the dynamic scan chains.

Abstract: An approach for representing integrated circuit device characteristics using polynomial equations involves analyzing integrated circuit device characterization data in a lookup table form and using an order incremental scheme to determine a polynomial equation of a relatively low-order that satisfies specified accuracy criteria. In situations where a polynomial equation that has an order less than a maximum allowable order cannot be determined, the integrated circuit device characterization data is partitioned into sub-domains and polynomial equations are determined separately for each sub-domain. The separate polynomial equations are then combined to generate a piecewise polynomial equation that represents all of the integrated circuit device characterization data.

Abstract: A tightloop method of timing driven placement. The present invention interleaves timing analyses and updates net weight based on the timing analyses as part of the cell location refinement processes of a placement algorithm. Thereby, the placement algorithm is augmented to factor in timing information such that the final placement is effective from overlap, net length, and timing perspectives.

Abstract: The present invention provides a tunable circuit for quickly optimizing an electrical field generated by the F-N tunneling operation. To optimize this electrical field, the charging of a positive charge pump is begun after the charging of a negative charge pump. The tunable circuit of the present invention provides a means to detect the optimal negative voltage at which pumping of the positive voltage should begin. The tunable circuit includes a resistor chain coupled between a first reference voltage and a negative voltage from the negative charge pump. When charging of the negative charge pump begins, a comparator compares the voltage at a node within the resistor chain to a second reference voltage. In accordance with the present invention, the node voltage within the resistor chain is equal to the second reference voltage when the negative voltage is equal to the voltage to be detected. Thus, the comparator generates a trigger signal when the voltage at the node decreases to the second reference voltage.

Abstract: Phase shifting generates features in a printed features layer, such as a printed circuit, that are narrower than the features on a fabrication layout, such as a mask, projected onto the printed features layer using the same optical system without phase shifting. Techniques for forming a fabrication layout for a physical design layout having critical features employing phase shifting include techniques for providing a layout for shifters. The techniques include establishing placement of multiple pairs of shifters for a set of critical features. A critical feature employs phase shifting. The set of critical features constitutes a subset of all critical features in a layout. After establishing placement of the pairs of shifters, phase information for the shifters associated with the set of critical features is assigned. This and related techniques expedite resolving phase-shift conflicts in fabrication layouts for phase-shifted features.

Abstract: A mask defect printability simulation server provides simulations, one-dimensional analysis, and reports to multiple clients over a wide area network, such as the Internet. This network-based simulation server allows a client to leverage a core of highly-trained engineers. Additionally, the network-based simulation server can be easily supported since only a single source for the tools associated with the simulation server is necessary for multiple clients. A client can access the simulation server using a standard personal computer having a browser, thereby eliminating the need for client to maintain an expensive database for the server. Finally, in the network-based simulation server, multiple users can view the same mask defect image and provide real-time comments to each other as simulation and analysis are performed on the defect image, thereby encouraging problem solving and decision-making dialogue among the users.

Abstract: An electrical alignment test structure enables monitoring and measuring misalignment between layers (or associated masks) of an IC. The alignment test structure comprises a target region and an alignment feature in different layers. The target region and the alignment feature may be formed in diffusion and polysilicon layers, respectively or in well and diffusion layers, respectively. In both embodiments, the alignment feature controls the size of a conductive channel in the target region. Misalignment can be checked by comparing channel resistance with a baseline (no misalignment) resistance. In another embodiment, the target region and alignment feature are formed in the diffusion and polysilicon layers, respectively, wherein the alignment feature controls the relative widths of the source and drain regions. Misalignment can be checked by comparing current flow with a baseline current.

Abstract: A low pass filter (LPF) is provided that smoothes and significantly slows any change in its input voltage. The capacitance of the LPF is provided by an NMOS transistor having its source and drain tied to ground. The resistance of the LPF is provided by a plurality of series-connected PMOS transistors. The gates of the PMOS transistors are coupled to ground and therefore these transistors are conducting. The PMOS transistors are fabricated in a floating well. Therefore, the LPF eliminates any capacitive coupling between a voltage supply and the well. Thus, any variation in the supply voltage fails to affect adversely the functioning of the PMOS transistors. Thus, the LPF of the present invention can advantageously smooth and significantly slow any change in its input voltage. In one embodiment, the input voltage is a reference voltage.

Abstract: A system and method for optimizing the production of lithography reticles involves identifying “proximity effect halos” around tight tolerance features in an IC layout data file. Features and defects outside the halos will not have a significant effect on the printing of the tight tolerance features. During reticle formation, the tight tolerance features and associated halos can be carefully written and inspected to ensure accuracy while the other portions of the reticle can be written/inspected less stringently for efficiency. The halo width can be determined empirically or can be estimated by process modeling. If an electron beam tool is used to write the reticle, a small spot size can be used to expose the tight tolerance features and the halos, whereas a large spot size can be used to expose the remainder of the reticle. A reticle production system can include a computer to read an IC layout data file, identify tight tolerance features, and define proximity effect halos.

Abstract: A structure and method are provided to ensure self-aligned fabrication of a tri-tone attenuated phase-shifting mask. A sub-resolution, 0 degree phase, greater than 90% transmission rim is provided along the edge of an opaque region. The alignment of this sub-resolution rim with the opaque and attenuated regions of the mask is performed in a single patterning step. In one embodiment, a narrow opaque region can be replaced by a sub-resolution, 0 degree phase, greater than 90% transmission line.

Abstract: A negative voltage detector including a resistor divider circuit is used to translate a negative voltage into a standard CMOS logic low or logic high value. The small area consumed by the negative voltage divider allows multiple device placement within a logic device without the consumption of much area on the logic device. Additionally, the multiple devices placed may detect different negative voltage thresholds with a simple tuning of device components.

Abstract: A method for generating a circuit design using specified input characteristics and desired output characteristics. An algorithm is used to generate candidate circuits from the desired circuit characteristics. The candidate circuit is tested with a stimulating test apparatus to provide actual output characteristics in response to the specified input characteristics. If the actual and desired output characteristics do not match, the candidate circuit is modified and re-tested. The design process may be automated or manual.

Abstract: An interface board and inserted modular IC interface cards allows variable length boundary scan chains. The chain can be constructed of any type of programmable integrated circuit (IC) in any order. The interface board contains a plurality of JTAG interfaces that respectively mate with standard adapter interfaces located on the modular IC interface cards. If less than the maximum number of modular IC interface cards are inserted into the interface board, a terminator card is inserted into the standard interface following the last modular IC interface card of the chain. The last test data output signal of the chain is routed back to a connector of the interface board. The interface board includes an output cascade connector that couples with an input cascade connector of another interface board so that any number of interface boards can be cascaded in series to expand the boundary scan chain.

Abstract: A game of tag using wireless devices is disclosed. In one embodiment of the present invention, players in a game space are each assigned a player to tag and assigned to another player to be tagged. Thus, each player is both “it” (trying to tag a target player) and a target (trying to evade being tagged). Interaction among players is conducted via wireless device.

Abstract: A method of fabricating a pack tray is provided wherein a plurality of modules are secured in a master frame. Each pack tray typically includes two types of modules: a chip module having an aperture therein to secure an integrated circuit chip and a pick-up module for picking up the pack tray. In one embodiment, all modules are identical in size. In another embodiment, the modules differ in size.

Abstract: A multimedia linking device automatically links user notations (e.g., handwritten notes) made on a page to time-varying data (e.g., audio). Consequently, a user can take notes while observing a multimedia presentation, for example, and later review the notes and the corresponding segments of the recorded multimedia presentation. This dynamic linking capability also enables a user to add new notes during playback, which are automatically linked to the segment of the multimedia presentation playing when the new notes are made. Similarly, new recordings can be appended to the multimedia presentation and they will be automatically linked to corresponding user notations. The user can also stop the playback of the recording and add new notes which are automatically linked to the segment of the multimedia presentation that was playing when the playback was interrupted.