Abstract: An integral modular cache. One embodiment includes a processor portion and a cache memory portion. The cache memory portion includes an array portion having tag logic and a set portion. The array portion extends along substantially all of a first axis of the processor. Control logic is to receive a cache size indicator and is capable of operating the cache with the one set portion or with additional set portions.

Abstract: A page closing method and apparatus for multi-port host bridges. According to a method disclosed, a plurality of memory access commands are received from a plurality of command ports. A command is selected from one of the command ports to be the next memory access command executed. A number of pages of memory are closed in response to the command selected as the next memory access command. The number of pages closed is determined at least in part on which command port provides the next memory access command.

Abstract: A dynamic feedback bias circuit. A system utilizing the dynamic bias circuit includes a first bus agent and a second bus agent. The first bus agent generates a first signal having a first voltage swing. The second bus agent has a core which operates at a core operating voltage, the core operating voltage having an amplitude less than the first voltage swing. The second bus agent has an input device which receives the first signal from the first bus agent. The input device of the second bus agent is biased by the dynamic feedback bias circuit to provide a core signal with a voltage swing approximately equal to or less than the core operating voltage.

Abstract: A method and apparatus for providing controllable compensation factors to a compensated driver circuit which may be used to perform testing of the structural integrity of the compensated driver circuit. One disclosed apparatus includes a compensated driver circuit having a number of subcomponents. At least one compensation factor, which may be provided by a compensation circuit, controls which of the subcomponents to enable. An additional circuit is coupled to provide controllable values for the at least one compensation factor.

Abstract: A heat exchanger. The heat exchanger includes a first heat dissipation mechanism having a first heat dissipation capacity and a second heat dissipation having a second heat dissipation capacity. At least one heat transfer mechanism thermally couples the first heat dissipation mechanism and the second heat dissipation mechanism to a heat generating component. The heat transfer mechanism has a limited conductivity portion in the thermal path to either the first or the second heat dissipation mechanism.

Abstract: An integral breakpoint detector. The integral breakpoint detector may be included in a processor, a chipset, or another bus agent. One embodiment is an apparatus such as an integrated circuit that includes a bus interface to communicate with a bus and an integrated breakpoint detector. The bus interface may include a bus tracker which communicates with the integrated breakpoint detector. The integrated breakpoint detector is to provide a first indication responsive to an occurrence of a predetermined relationship between a programmable value and a condition related to the bus.

Abstract: A heat exchanger adapated for heat dissipation. A first heat transfer element has an end which forms an engaging surface. A second heat transfer element has a receptacle portion which is integrally formed and has an engaging surface that is urged against the engaging surface of the first heat transfer element when the first heat transfer element and the second heat transfer element are mated.

Abstract: A method and apparatus for source synchronous transfers at frequencies including an odd fraction of a core frequency. A disclosed apparatus includes a signal driver circuit and a strobe signal driver circuit. The signal driver circuit is coupled to generate a cycle for a first signal at a first frequency from a core signal from a core operating at a core clock frequency that is an odd fractional multiple of the first frequency. The strobe signal driver circuit is coupled to generate a strobe signal at an intermediate point of the cycle to allow latching of the first signal triggered by the strobe signal.

Abstract: A method and apparatus which may be used for control of the rate of change of current consumption of an electronic component. The apparatus includes a processing circuit having coupled to receive a throttling signal that throttles operation of the electronic component. The apparatus also includes a power management circuit which detects a power consumption change of the processing circuit generates the throttling signal in response to the power consumption change event.

Abstract: A fan for a computing device. The fan includes a motor and a blade portion having a plurality of blades; however, the blade portion is located apart from the motor. A blade driving mechanism connects the motor to the blade such that the blade rotates when the motor is operating.

Abstract: A method and apparatus for handling cache snoop errors. According to one method disclosed, a snoop cycle having a snoop address is generated by a first bus agent. A second bus agent detects a snoop error in response to that bus cycle. As a result of the detected snoop error, the snoop error is signaled to the first bus agent, the bus agent which generated the snoop cycle.

Abstract: A heat generating component such as a microprocessor, in a small form factor, low profile electronic device such as a laptop computer is cooled by using an elongated hollow heat exchanger with a fan at one end of the heat exchanger. A heat pipe, having two ends, has one end thermally coupled to the heat exchanger and the other end thermally coupled to the heat generating component. A heat sink thermally coupled to the other end of the heat pipe, in thermal contact with the heat producing component may be used. In a laptop computer having a four vertically extending side walls including a front wall a back wall and two side walls where the heat generating component is a microprocessor, the heat exchanger can extends in a direction adjacent and parallel to one of the side walls, with an air outlet formed in one of said front and rear walls and an air inlet in the other of said front or rear walls or the side wall to which the heat exchanger is adjacent.

Abstract: A fan for a computing device. The fan includes a motor and a blade portion having a plurality of blades; however, the blade portion is located apart from the motor. A blade driving mechanism connects the motor to the blade such that the blade rotates when the motor is operating.

Abstract: A short write test circuit and mode. One disclosed apparatus includes a memory cell that is connected to a first bit line and a second bit line. The short write test circuit causes a short write having a programmable duration to stress the memory cell.

Abstract: A method and apparatus interconnecting multiple devices on a circuit board. One disclosed circuit board has a first attach region on a first surface for coupling a first set of pins from a first device to a set of signal lines. A second attach region on a second surface is for coupling a second set of pins from a second device to the set of signal lines. The second attach region is predominantly non-overlapping with respect to the first attach region.

Abstract: A method and apparatus for restoring a memory device channel when exiting a low power state. One method involves storing a set of memory initialization values from storage locations in a memory controller into a memory that maintains values during a power down state. The values may be necessary to access a system memory. When the power down state is exited, the values are restored to the storage locations in the memory controller.

Abstract: A method and apparatus for configuring and/or initializing memory devices. A disclosed method initializes a memory controller and a plurality of memory controller configuration registers. Serial identification numbers are assigned to memory devices coupled to the memory controller. Additionally, groups of device identification numbers, which are based at least in part on the memory device sizes, are assigned to the memory devices, and the memory devices are enabled.

Abstract: A heat pipe with pumping capabilities and use thereof in cooling a device. One embodiment of the heat pipe has an internal pumping mechanism that provides an enhanced capillary flow within a chamber of the heat pipe.

Abstract: A method and apparatus for throttling high priority memory accesses. An apparatus of the present invention includes an arbiter circuit and a throttling circuit. The arbiter circuit is coupled to receive first and second types of memory access commands and has a preference for the first type of memory access commands. The throttling circuit is coupled to the arbiter and can at least temporarily reduce the preference for the memory access commands of the first type.

Abstract: A page closing method and apparatus for multi-port host bridges. According to a method disclosed, a plurality of memory access commands are received from a plurality of command ports. A command is selected from one of the command ports to be the next memory access command executed. A number of pages of memory are closed in response to the command selected as the next memory access command. The number of pages closed is determined at least in part on which command port provides the next memory access command.