Abstract: An electronic component having a flexible substrate with conductive traces thereon may have the leads separated into arrays that are shaped to contact and be surface mounted to the bonding lands on a printed circuit board (PCB). The flexible substrate, such as polyimide, adheres to the traces and is formed into lead arrays with them. The lead arrays thus keep portions of the leads and the outer bonding areas corresponding thereto aligned with respect to each other during handling and mounting to the PCB. An alignment mechanism may be optionally present on the lead arrays that mates with a corresponding mechanism on the PCB. The package body itself may be overmolded, assembled from prior parts, etc. Another alternative version includes test points on the perimeter of the substrate beyond the outer bonding areas that may be used to test the device, such as an integrated circuit chip or die, at an intermediate stage in the assembly process.

Abstract: A method for fabricating and especially for encapsulating a semiconductor device in a plastic package is disclosed. In accordance with one embodiment of the invention the method includes steps of providing an encapsulation mold having a first chamber and a second chamber, with the second chamber spaced outwardly from and substantially surrounding the first chamber. The first chamber is shaped to receive a removable insert. An insert is selected for the particular body type and style which is desired and that insert is secured in the first chamber. The insert has a cavity which is shaped to define the desired encapsulated device package body. A lead frame is provided including a bonding area and a plurality of leads, each lead having a inner portion near the bonding area and an outer portion extending outwardly from the bonding area.

Abstract: An electronic pad array carrier IC device for mounting on a printed circuit board (PCB) or flex circuit substrate has a thin, flexible "tape" substrate having a plurality of traces. The substrate may be a polyimide or other material that can withstand relatively large lateral mechanical displacement. An integrated circuit die is mounted in proximity with or on the substrate and electrical connections between the integrated circuit chip and the traces are made by any conventional means. The substrate traces are provided at their outer ends with solder balls or pads for making connections to the PCB. A package body covers the die, which body may be optionally used to stand off the package a set distance from the PCB so that the solder balls will form the proper concave structure. Alternatively, a carrier structure may be provided around the periphery of the substrate to add rigidity during handling, testing and mounting, but which may also provide the stand-off function.

Abstract: A molded package having reduced unintentional and undesirable mold flash or bleed around an exposed heat sink is provided through the use of a compression structure within the package. The compression structure may be integral with a heat sink, die bond flag, if one is present, or may be a separate structure, which extends from a die support surface of the heat sink to the opposite side of the mold. During molding, the compression structure presses a heat dissipation surface of the heat sink against the mold surface forming a tight seal to prevent the mold compound from creeping around between the mold and the heat dissipation surface to form flash. The heat sink may also be provided with adhesion promotion features along its side to improve the physical bond or attachment between the heat sink and the plastic body of the package.

Abstract: A process for the fabrication of CMOS devices is disclosed in which a selectively doped silicon layer is selectively oxidized to provide a differential thickness in the silicon and in the overlaying silicon oxide. In accordance with one embodiment, a semiconductor substrate is provided having a layer of silicon overlaying a surface of that substrate. A first area of the layer of silicon is selectively doped with N-type impurities while a second area is left undoped. The silicon is thermally oxidized to form a thermal oxide having a greater thickness over the N-type doped area than over the undoped area. Correspondingly, the silicon under the thick thermal oxide has a lesser thickness than the silicon under the thin thermal oxide. The layer of silicon is patterned to form gate electrodes and interconnects, with some of the gate electrodes formed from the silicon having N-type dopant and some of the gate electrodes formed from the silicon which is not doped N-type.

Abstract: A lead frame having multiple layers permits fine connection to a large number of bonding pads on an electronic component such as an integrated circuit (IC), but strong external package leads. A fully featured or completely extensive lead frame layer bears proximal ends that may be finely dimensioned for connection with the bonding pads of an IC. A second frame layer is laminated with the first layer, but does not have proximal ends that extend as far as those of the fully featured frame layer. The doubled external leads for mounting to a printed circuit board (PCB) are relatively stronger than the single, more finely featured proximal lead ends that are bonded to the component. The lead frame layers may also differ with respect to their thicknesses, electrical conductivity, strength and solder-wetting characteristics.

Abstract: A package for containing high performance electronic components, such as high speed integrated circuits (ICs). The package bears a substrate of multiple layers having a cavity therein. Leads may be placed within holes in the substrate and soldered or otherwise electrically connected to conductive patterns or layers in the substrate. A thermally conductive insert is attached to one side of the substate. The insert has a pedestal which protrudes through the cavity in the substrate. An electronic component, such as an IC may then be mounted on the pedestal and electrically connected to a conductive metal pattern on one of the layers of the substrate. This assembly may then be coated with a dielectric material to form the package body, leaving the distal ends of the leads and the back side of the insert exposed.

Abstract: A process for fabricating semiconductor devices is disclosed which utilizes a selective deposition process to reduce the total number of process steps and especially the total number of photolithography steps required. In accordance with one embodiment of the invention a semiconductor substrate is provided having an insulating layer, a nucleating layer, and a second insulating layer overlaying the substrate. A photoresist mask is used an implant mask and as an etch mask to expose a portion of nucleating layer. A second implant mask is formed by the selective deposition of tungsten or other material on the exposed nucleating layer. The selectively deposited material is then used a mask for a second implantation.

Abstract: A semiconductor device, device metallization, and method are described. The device metallization, which is especially designed for submicron contact openings, includes titanium silicide to provide a low resistance contact to a device region, titanium nitride and sputtered tungsten to provide a diffusion barrier, etched back chemical vapor deposited tungsten for planarization, and aluminum or an aluminum alloy for interconnection.

Abstract: A process is disclosed for the fabrication of semiconductor devices which yields a device having a very short effective channel length and having polycrystalline source and drain electrodes. In accordance with the disclosed process, a semiconductor substrate is provided having a masking element positioned on the substrate surface. A layer of polycrystalline silicon is deposited on the exposed areas of the substrate surface by the process of selective deposition. The selectively deposited polycrystalline silicon is doped with conductivity determining impurities and that impurity material is thereafter redistributed to dope the underlying substrate to form source and drain regions. The masking element is removed to expose the portion of the semiconductor surface between the source and drain regions and to allow for a subsequent optional channel implantation.

Abstract: A process is disclosed for fabricating bipolar transistors having self aligned and closely spaced polycrystalline silicon base and emitter electrodes. The process is especially amenable to integration with the fabrication of MOS transistors to form BiMOS integrated circuits. In accordance with one embodiment of the invention, a P type polycrystalline silicon layer is deposited overlying an N type silicon substrate. The polycrystalline silicon layer is patterned to form base contact electrodes and to leave exposed a portion of the surface of the N-type substrate. An electrically insulating layer is formed overlying the polycrystalline silicon base contacts and the exposed silicon substrate. Sidewall spacers are formed on the electrically insulating layer at the sidewalls of the base contact electrode.

Abstract: A high density DRAM having a plurality of cells each including a storage capacitor and a single control FET formed together in a trench to substantially reduce planar area of the cell. The FET drain is formed in the upper portion of a pedestal and is accessible externally through a metal line, which reduces line resistance and capacitance. Field oxide is included to isolate capacitors and reduce leakage and breakdown.

Abstract: An automatic system for the inspection of surfaces of an object employing computer vision. The system examines the uniformity of the surface and adds it to the negative of an ideal mask, and then thresholds the result to determine if the object is defective or not. A binary image showing only the defects is generated by the system. The system ignores surface features, such as locating notches or markings that are intentional, by "fitting" them with their morphological negatives. Small electronic packages, such as integrated circuit plastic packages (e.g. dual-in-line packages or DIPs), can be accurately inspected by the system. The system provides an objective, fast and economical method of inspecting objects.

Abstract: A semiconductor device structure including a contact and a method for its fabrication are disclosed. In accordance with one embodiment of the disclosure, a contact is formed between a monocrystalline silicon substrate and an overlying silicon layer. A silicon substrate is provided which has a first insulating layer formed thereon. A layer of silicon is deposited and patterned over the insulator layer. The patterned silicon layer is then oxidized and a contact opening is etched through the first insulator layer and the silicon dioxide is expose portions of the silicon substrate and an adjacent portion of the patterned silicon layer. A further layer of polycrystalline silicon is then selectively deposited onto the exposed portions of the substrate and silicon layer to form an electrical connection between the two.

Abstract: A process for fabricating an integrated circuit resistor is disclosed. In accordance with one embodiment of that invention a first thin layer of silicon is deposited to overlay a semiconductor substrate. That thin layer of silicon is doped to a predetermined level to establish the proper conductivity desired for the integrated circuit resistor being formed. The first layer of silicon is patterned to form a first resistor layer and a second interconnect area with the two areas being in contact. A layer of insulating material is formed over the resistor area to mask the resistor area from subsequent processing steps. A second layer of silicon is deposited by a process of selective deposition onto the exposed interconnect areas of the first thin layer of silicon and that selectively deposited silicon is heavily doped with conductivity determining impurity material to reduce the resistivity thereof.

Abstract: A process for the fabrication of elevated source/drain IGFET devices is disclosed. In accordance with one embodiment of the process, a silicon substrate is provided which is divided into active and field regions by a field oxide. A gate oxide is formed over the active region and a thin layer of polycrystalline silicon and a thick layer of silicon nitride are deposited on the gate oxide. The polycrystalline silicon and the silicon nitride are etched to form a stacked structure, with the spacers having substantially the same height as the stacked structure, in the pattern of the gate electrode. Sidewall spacers are formed on the edges of the stacked structure and the silicon nitride is removed. Polycrystalline silicon is then deposited onto the polycrystalline silicon and the exposed portions of the source and drain regions to complete the gate electrode and to form the source and drain electrodes.

Abstract: A process for forming n- and p-wells in a semiconductor substrate wherein each well has a shallow, highly-doped surface layer whose depth may be independently controlled. This high/low doping profile for a twin well CMOS process may be produced using only one mask level. The method provides high/low impurity profiles in each well to optimize the NMOS and PMOS active transistors; provides close NMOS to PMOS transistor spacing; avoids a channel-stop mask level and avoids a threshold adjustment/punchthrough mask level.

Abstract: Metal-oxide-semiconductor (MOS) transistors with n-type source/drain regions also having germanium-doped regions in or near the source/drains. The presence of germanium near or at the location of phosphorus in graded source drains (GSDs), lightly doped drains (LDDs) and double diffused drains (DDDs) gives a better profile of the drain region with a reduced junction depth than that obtainable with phosphorus or particularly phosphorus and arsenic together. Good grading of the drain junction to avoid hot carrier instability or hot carrier injection problems is obtained along with shallow source junctions, which minimizes lateral dopant diffusion and decreases the distance between n.sup.- and n.sup.+ regions in GSDs and LDDs.

Abstract: A semiconductor device, device metallization, and method are described. The device metallization, which is especially designed for submicron contact openings, includes titanium silicide to provide a low resistance contact to a device region, titanium nitride and sputtered tungsten to provide a diffusion barrier, etched back chemical vapor deposited tungsten for planarization, and aluminum or an aluminum alloy for interconnection.

Abstract: A compact CMOS structure and method for fabricating the structure are disclosed. In one embodiment of the invention the structure includes a P-type surface region in a silicon substrate surrounded by a field oxide which extends, at least in part, above the surface of the substrate. A polycrystalline silicon sidewall frame is formed at the sidewall of the field oxide and a gate insulator is formed over both the polycrystalline silicon frame and the silicon surface region. A common gate electrode is formed which traverses the frame and the surface region. P-type source and drain regions are formed in the polycrystalline silicon frame on opposite sides of the gate electrode and N-type source and drain regions are formed in the surface region on opposite sides of the gate electrode.