Abstract: A polycrystalline silicon electrode and method for its fabrication are disclosed. The electrode includes a barrier layer formed by the implantation of carbon, nitrogen, or oxygen ions between two layers of polycrystalline silicon. The lower layer of polycrystalline silicon is lightly doped or undoped and the top layer is heavily doped to increase the conductivity of the electrode. The barrier layer impedes the diffusion of conductivity determining dopant impurities from one layer of polycrystalline silicon to the other.

Abstract: A lithography method for forming an opening in a resist layer with a sloped profile is disclosed which requires no additional processing steps or equipment. A scattering element, for example a ground glass diffuser, is placed in the optical path of radiation passing through a standard lithography apparatus. The scattering element modifies the radiation passing through the lithography apparatus with the result that the developed resist profile exhibits sloped edges. The slope modification can be conveniently changed by exchanging the optical scattering element used.

Abstract: A method for handling semiconductor components by utilizing a removable filler strip for temporarily securing or clinching longitudinally arrangeable individual components in a tube, rod or hollow magazine. The filler strip is generally flat, but has surface features that serve to press the components against the top, bottom or side of the tube. Partial removal of the filler strip will result in the dispensing of some of the components while the remainder are retained by the filler strip in the tube.

Abstract: An electronic device package on a lead frame with a peripheral carrier structure holding the distal ends of the leads in rigid position. The carrier structure is spaced apart from the package body and permits the package to be handled and tested while protecting the leads. A different, relatively lower quality and less expensive material is used for the carrier structure than for the package body to reduce the cost of the package since the carrier structure may comprise several times, for example four times or more, the volume of the package body.

Abstract: An improved LOCOS device isolation method for forming a field oxide is disclosed having the advantage of controllable and uniform sidewall framing of a nutride oxidation mask. This advantage is achieved by the use of a polysilicon layer overlying a nitride mask with the polysilicon providing an etching endpoint during the anisotropic etching used for sidewall formation. In one embodiment of the invention a silicon substrate is provided having a pad oxide formed on its surface and a first polysilicon stress-relief buffer layer formed overlying the pad oxide. A first nitride layer, to be used for oxidation masking during field oxide growth, is deposited overlying the first polysilicon layer. Next, a second polysilicon, etch-resistant buffer layer is deposited overlying the first nitride layer.The first nitride layer and second polysilicon layer are patterned by conventional lithography while the first polysilicon and pad oxide layers remained unpatterned.

Abstract: A process for fabricating high-capacitance trench capacitors in a lightly doped, shallow well of a semiconductor substrate. The process involves a two-step doped glass deposition/diffusion routine. After trench formation into a shallow, lightly doped well, a first doped glass is deposited inside the trench and the dopant is diffused from the glass through the trench interior surface to form a region or halo of extra doping around and below each trench. A second doped glass deposition and diffusion of an impurity of the opposite conductivity type to a shallow depth on the trench wall surfaces provides a p/n junction with the first diffusion region to increase the capacitance of the subsequent capacitor. In addition, the trench devices are better isolated from each other, the substrate and any adjacent devices.

Abstract: A process for forming n- and p-wells in a semiconductor substrate wherein each well has a shallow, highly-doped surface layer whose depth may be independently controlled. This high/low doping profile for a twin well CMOS process may be produced using only one mask level. The method provides high/low impurity profiles in each well to optimize the NMOS and PMOS active transistors; provides close NMOS to PMOS transistor spacing; avoids a channel-stop mask level and avoids a threshold adjustment/punchthrough mask level.

Abstract: A multiple element integrated circuit trench cell having at least one vertical field effect transistor (FET) in a wall of a trench in a semiconductor substrate. The cell further comprises a central load device within the trench which is electrically connected to the vertical FET. The central load device may be an active load device, such as another field effect transistor, or a passive load device, such as a resistor. Additionally, a further FET may be present in another wall of the trench or in a lateral orientation adjacent the trench in the semiconductor surface. Two of these multiple element trench cells may be interconnected in various configurations to form conventional static random access memory (SRAM) cells.

Abstract: A method for forming multiple-component thin films using a separate ion cluster beam (ICB) source for each component. Stoichiometry control is provided by measuring the extraction currents across an acceleration voltage and controlling the component supply to the ICB source. The ion clusters are broken up into an atomic beam by microwave energy. If superconducting films are made, the atomic beams are passed through an oxygen plasma also generated by microwave energy to maximize oxygen incorporation into the thin film. The oxygenated atomic metal ion beams are focused onto a common substrate to form the multiple component thin film. Oxygen is kept away from the ICB sources by differential pumping seals.

Abstract: A process for fabricating a CMOS device using one sidewall spacer for both the source/drain implant and salicide formation, thereby providing an improved salicided source/drain structure. The use of one sidewall spacer for both the source/drain implant and the silicide formation facilitates the closer spacing of the silicide region to the gate edge. Prior to the salicidation, a silicon overetch is performed to remove the P+ implant in the source/drain and poly regions of the NMOST. The silicon overetch forms a concave surface on the N+ source/drain regions, which allows salicide formation closer to the edge of the channel. Due to the proximity of the edge of the silicide to the edge of the channel, the series resistance of the NMOST is significantly reduced.

Abstract: An erasable programmable read only memory (EPROM) cell having a floating gate and a control gate where the floating gate and the control gate are deliberately offset or asymmetrical from the source/drain and drain/source regions in the substrate. During programming, the source region is the one spaced apart from the gates while the drain region is aligned thereto. This orientation produces high gate currents to provide faster programming. During a read operation the aligned region now becomes the source and the spaced apart region becomes the drain to provide high drain currents for fast access. The asymmetrical EPROM cells of the present invention may be readily made using conventional spacer technology.

Abstract: A process is disclosed for the selective oxidation of MOS devices which preferentially removes implanted field doping from selected silicon substrate regions. In one embodiment, a CMOS substrate is provided with an overlying layer of silicon oxide and a layer of polycrystalline silicon. Active and field regions are defined in each of the CMOS device regions. A blanket boron implantation dopes both the N-type and P-type field regions. The N-type field region is selectively oxidized at a greater oxidation rate than is the P-type field region to cause a greater segregation of boron impurities into the growing oxide over the N-type field region. Regions of enhanced boron doping are thus formed under the field oxide in the P-type region, but not in the N-type region.

Abstract: Metal-oxide-semiconductor (MOS) transistors with n-type source/drain regions also having germanium-doped regions in or near the source/drains. The presence of germanium near or at the location of phosphorus in graded source drains (GSDs), lightly doped drains (LDDs) and double diffused drains (DDDs) gives a better profile of the drain region with a reduced junction depth than that obtainable with phosphorus or particularly phosphorus and arsenic together. Good grading of the drain junction to avoid hot carrier instability or hot carrier injection problems is obtained along with shallow source junctions, which minimizes lateral dopant diffusion and decreases the distance between n- and n+ regions in GSDs and LDDs.

Abstract: An electronic device package on a lead frame with a peripheral carrier structure holding the distal ends of the leads in rigid position. The carrier structure is spaced apart from the package body and permits the package to be handled and tested while protecting the leads. A different, relatively lower quality and less expensive material is used for the carrier structure than for the package body to reduce the cost of the package since the carrier structure may comprise several times, for example four times or more, the volume of the package body.

Abstract: A filler strip for temporarily securing or clinching longitudinally arrangeable individual components in a tube, rod or hollow magazine. The filler strip is generally flat, but has surface features that serve to press the component against the top, bottom or side of the tube to prevent the component from knocking against adjacent components and cracking, chipping or otherwise damaging one or more of the components. The filler strip is particularly suited to eliminating the knocking motion of expensive ceramic integrated circuit packages that are shipped and handled in transparent plastic tubes or rails.

Abstract: A salicided twin-tub CMOS process using germanium implantation to retard the diffusion of the dopants, such as phosphorus and boron. Implantation of n+ and p+ dopants after titanium salicidation is employed to fabricate devices with low junction leakage and good short-channel effects. Also, the germanium dopant may be introduced before or after the formation of the refractory metal silicide formation, and may be implanted independently or together with the dopant whose diffusion in the silicon it will modify. The employment of germanium permits the use of a phosphorus implant through a relatively thick refractory metal silicide contact layer. If arsenic is implanted through the silicide layer to solve the deep junction problem, the silicide layer must be thin to permit the passage of the larger arsenic atoms typically stopped by the silicide. Thinner silicide layers have the disadvantage of higher sheet resistances.

Abstract: A random access memory (RAM) cell of a trench within a semiconductor substrate. The RAM cell has a load device in the form of a sidewall around at least part of the perimeter of the trench. The load device should be connected to either one of the source/drain regions or the gate in a field effect transistor (FET). If the load device is a capacitor, using the sidewall structure as one plate and the wall of the trench as the other plate, with a thin dielectric layer between, then a dynamic RAM cell (DRAM) cell with result. On the other hand, if the sidewall load device is a resistor, then a static RAM cell or SRAM will result. The compact nature of the trench sidewall load structure will consume appreciably less lateral space than conventional RAM cells. Additionally, the gate for the FET in the bottom floor of the trench can be formed at the same time and out of the same conductive layer as the conductive sidewall load device, an advantage which saves process steps.

Abstract: A lead frame having a central die bond flag for ceramic integrated circuit die packages. The direct connection of the die bond flag to the lead frame via one or more leads permits direct connection of the back side or substrate of an integrated circuit die to a lead while eliminating dedicated supports that provide physical support but no electrical lead function. In a particular embodiment of the invention, a lead frame is provided whereby any of the leads may be chosen to serve as the die bond flag support/lead combination, whereby the rest of the leads are severed from connection with the die bond flag.

Abstract: A method is disclosed for fabricating a semiconductor device and especially for contacting a semiconductor device. A silicon substrate is provided which has a device region formed at the surface thereof and which is contacted with a silicide. An insulating layer overlies the substrate and has an opening therethrough which exposes a portion of that device region. Titanium nitride is deposited in a blanket layer overlying the silicide and the insulating layer. A leveling agent such as a spin-on glass is applied to the structure to substantially fill the opening. That leveling agent is then anisotropically etched to leave the leveling agent only in the opening. The leveling agent is used as an etch mask to remove the portion of titanium nitride which is located outside the opening. After removing the remaining leveling agent, the titanium nitride in the opening is used as a nucleating surface for the selective deposition of a tungsten plug which fills the contact opening.

Abstract: A technique for selectively implanting regions of semiconductor crystals with oxygen to increase their yield strength. This intentional, selective oxygen pinning technique is especially useful in causing underlying, originally oxygen-free silicon to be more resistant to plastic deformation during isolation field oxide formation processes. Oxide regions grown on a substrate cause stress at the oxide/substrate interface and typically dislocation and other stress induced crystallographic defects at and near the point of stress, especially if the substrate is essentially oxygen-free. Dislocation and other crystallographic defects that occur in the areas of device formation and p/n junctions can cause junction leakage and active device degradation.