Abstract: Auto-adaptive method of load balancing in a data transmission system wherein one active station (32) amongst a plurality of stations requests the access to the resources of a host (10), the active station being connected to a connected-oriented network linked to host (10) by means of a plurality of communication controllers (12, 14, 16) identified by the station (32) with the address of host (10), the connected-oriented network implementing a protocol in which route discovery frames are sent from the station (32) to all the communication controllers (12, 14, 16) and response frames are sent back with a predefined delay from each one of the communication controllers to the station (32), whereby the station (32) selects the route defined by the first received response frame, this method being characterized in that the delay to apply to the response frame is at each moment dynamically defined by using a logarithmic function of the current number of active stations.

Abstract: The ATM bus (100) is composed of a clock signal, CLK, a synchronization signal, -SYNC, a data bus, S(0-31), and an adapter identification bus, SID(0-3). It is a synchronous bus running at any clock rates. The clock signal is generated by the backplane (20) and transmitted to each adapter (10-1, . . . 10-N). During each clock cycle, the data bus has three serialized operation modes (or cycles) defined in this order: a bus_req cycle of 1 clock period, a bus_ack cycle of 1 clock period and an ATM cell_xfr cycle of 14 clock periods. The free-running synchronization signal is generated on the backplane (20) and transmitted to each adapter (10-1, . . . , 10-N). The activation of the synchronization signal of one bit of the data bus, S(0-31), starts the bus_req cycle. In each case, the remaining data bus signals are left in high impedance state. To increase the bus performance, the synchronization signal is held active until an adapter activates its bus_request signal.

Abstract: A system and method for converting a window based data link flow control to a rate based flow control. In addition to the conventional data link control window, a second window is established under control of an adaptive committed information rate (ACIR). When either the DLC window or the second window is closed information frames are queued. The second window is closed when a frame exceeds the burst size authorized in the ACIR.

Abstract: A cache based processing system is provided with a loop detection circuit for detecting the entry into and termination of program loops and for enabling peripheral device access to the main memory after completion of the first pass through the loop and terminating access when the program leaves the loop.

Abstract: The present invention discloses a method and a system for performing fast division using non linear interpolation. A storage stores x-axis and y-axis coordinates (X0, Y0) of a plurality of non uniform interpolation points, and x-axis and y-axis coordinates (&Dgr;X, &Dgr;Y) representing the differences between two successive points of the plurality of non uniform interpolation points is used. The plurality of non uniform interpolation points is selected such that the x-axis difference (&Dgr;X) is a power n of 2 in the form of (&Dgr;X=2n), with n being an integer. Upon reception of an input operand X, the storage selects and outputs a set of coordinates (X0, &Dgr;Y, n, Y0) associated to the input operand.

Abstract: A method and system for prefetching data from storage and storing the data in a cache memory for use by an executing program includes means for detecting when a program has entered a processing loop and has completed at least one pass through the processing loop. At the completion of one pass through the processing loop, determining the requirement for additional data and prefetching the required data. Monitoring the operation of the program to detect termination of loop processing and terminating the prefetch of data from storage until the detection of a subsequent program loop.

Abstract: The Committed Information Rate (CIR) functionality is converted to an Adaptive Rate Base (ARB) mechanism. The solution is based on the interaction between a proactive setting of the Explicit Congestion Notifications (ECN) in the Frame Handler (FH) function of the switches and a converging Adaptive CIR algorithm in the Terminal Equipments. The result of this interaction is that when a logical bottleneck is in the process of settling in a switch, the CIR at the Terminating Equipment adapts itself to the throughput of the forming logical bottleneck. Henceforth, the logical bottleneck is exported at the boundary of the network within the Terminating Equipment. The end result is that the data sent by the data link control in the Terminating Equipment is paced so that the output matches that of the weakest point in the network, keeping it busy but not congested.

Abstract: The connecting device includes a securing plate and locking spring attached to the cable connector of the cable-to-card connectors. The connecting device is pressed, when the connectors are mated, by the front portion of the cable connector against the host machine chassis which in turn is pressed flat against the adapter card brackets. In a preferred embodiment the connecting device is attached on the front portion of a standard cable connector with removable fastener, in particular with a locking spring. In another embodiment, the connecting device is an integral part of the cable connector.

Abstract: A method and apparatus for an isochronous traffic of Asynchronous Transfer Mode (ATM) cells in a ring network having at least two stations (101,102) and a ring server (001). The communication within the ring is based on specific isochronous control and data cells. The control cell contains a cell header, sequence number, type of command and parameter fields. The data cell contains a header and a payload divided into N m-bit slots. The isochronous data cells are shared by a plurality of stations on the ring by allocating corresponding slotlist whose identification is carried in the parameter field. Furthermore, the server provides for each station's communication link a transmit identifier in the header associated to a reference in a list of allocated slots for transmission and a receive identifier associated to a reference in a list of allocated slots for reception.

Abstract: A LAN adapter for transferring data frames from a LAN to memory buffers in a processor in which the LAN driver follows either the ODI or the NDIS specification. The adapter accumulates the frame length and compares this to the storage capacity of the buffer. If the frame length does not exceed the buffer capacity and the LAN driver implements the ODI specification, the adapter will indicate good status to the driver. If the frame length exceeds the buffer capacity the adapter will either send bad status to the ODI driver or reuse the buffer and send no status. If the driver follows NDIS, status is sent at the end of the frame.

Abstract: A method for transferring data between non-contiguous buffers in a memory and an I/O device via a system I/O bus uses a descriptor queue stored in memory. Each descriptor points to a buffer and includes the length of the buffer. The I/O device is provided with the base address of the queue, the length of the queue and a current address which at initialization is the same as the base address. When data is to be transferred a device driver located in the processor sends the number of available descriptors (DescrEnq) to the I/O device which accesses the descriptors individually or in burst mode to gain access to the data buffers identified by the descriptors.

Abstract: A DMA Controller, in response to a data transfer request from a slave device, initiates a memory transfer cycle and informs the slave device when the data transfer has completed. In order to avoid dead clock cycles on internal bus(es), the DMA Controller initiates a speculative data transfer cycle after the notification. The DMA Controller aborts the speculative data transfer cycle if the slave device does not request another data transfer within a predetermined time.

Abstract: A multimedia display system includes a central processing unit, a storage device associated with the central processing unit, a standard interface bus to which the central processing unit and the storage device are connected, a graphics processor connected to the bus for generating graphics data in response to commands from the central processor, a digitizer for converting an analog video signal to digital form and for producing synchronization signals, a video processor for processing the digitized video data to produce pixel representations of the digitized video signal, a shared frame buffer for storing the graphics data generated by the graphics processor and the pixel representations of the video signal, a device for converting the stored digital data to a data stream appropriate for driving a video monitor, and a video monitor for displaying the graphics data and the video information, wherein the video processor generates a programmable variable phase vertical synchronization signal for synchronizing v

Abstract: An integrated D/A converter has a first feedback circuit for generating a first bias voltage to compensate for systemic changes. A second feedback circuit includes a plurality of switchable current sources biased by the first bias voltage and controlled by an externally supplied attenuation control signal to generate a second bias voltage which is applied to control the D/A current sources.

Abstract: A method and apparatus for detecting the absence of an activity or event during a time period D divides the time period D into N equal time sub-periods. A register is reset upon the occurrence of an event or activity. The register is incremented at the end of each sub-period and examined to determine if it exceeds the value N in which case there has been no activity during the time period D. The precision of the measurement is regulated by increasing or decreasing the value of N and the sub-periods are determined by dividing D by N.

Abstract: A communication adapter connected between a communication line and a host processor segments a received data frame by storing the received data in a buffer chain made up of equal length buffers. As each buffer is filled, the adapter interrupts the host. The host moves the data stored in the filled buffer into its own storage. It interrupts the adapter so that the buffer can be returned to the chain of free buffer and completes transmission protocol processing before the entire frame is received. If the frame has been received without error or buffer overrun it is delivered to the user immediately after transfer of the last buffer.

Abstract: A temperature compensated resistance current generator. The generator provides temperature compensated reference current in a digital CMOS environment where resistors with positive temperature coefficients are not available, and where temperature coefficients are large. The current generator has two current sources and a subtraction circuit which subtracts the current from one current source from the current from the other current source to create a primary current. A proportionality circuit multiplies the primary current by a constant to produce the generator output.

Abstract: An audio system is provided for generating audio sound for a host computer. It includes an interface connector for connection with the host computer; an interface controller for communicating with the host computer using the interface connector; a trap adapted to trap audio instruction signals from an application running on the host, such as a game having an audio portion; a trap controller adapted to control the trap; and an audio output. The system operates with an interface communicator which is adapted to respond to a request from the interface controller to read information from the trap and send audio output instruction to the audio output to generate audio sound.

Abstract: A hot-plugging circuit associated with a backplane or motherboard for controlling the rate of application of voltage and current to a non-operating printed-circuit card in the process of being inserted into a backplane connector in a system including other already-operating printed-circuit cards. Each backplane connector has connector contacts of two different lengths. An isolation diode at each connector is connected to two of the longer contacts of the connector and is forward biased by a non-operating printed-circuit card being inserted into that connector. The forward-biased isolation diode triggers a card insertion circuit to recognize that a non-operating printed-circuit card is in the process of being inserted. The card insertion circuit triggers a voltage and current control circuit to ramp up the voltage and current furnished to the non-operating printed circuit.

Abstract: In a token ring network a periodic recirculating frame having a plurality of information carrying slots and a header section is used for enabling a plurality of telephone stations to exchange information carrying signals. The header is provided with a token which can assume one of three states. In the first state FF, a telephone station wanting to make a call, changes the token to the second state 00 and inserts call establishment information in the header. A server station also connected in the ring detects the second state as a request to establish a connection from and to a station specified in the header. The server changes the token to the third state AA and inserts a slot assignment in the header. All stations receiving a frame with a token in the third state examine the header. The calling station implies confirmation of the requested connection and the called station is made aware of the call and the identity of the caller.