Abstract: A method of transmitting digitized voice signals as packets of bits in a digital transmission network to which a plurality of terminals acting as sources of voice signals are attached. The method includes, at the transmitting end and for each source, the steps of: a dividing the signal into successive, digitally-coded segments; performing a so-called source activity detection; and assembling the bits resulting from the coding operation into packets, each packet being provided with a header containing, in particular, a parity bit whose logic value is modified whenever an inactivity or long pause is detected. At the receiving end, detection of a change in the value of said parity bit causes the delivery of a packet of bits to the decoder/synthesizer to be delayed by a given time interval called retention delay.

Abstract: A listener echo canceller for a receiver made to receive data symbols a.sub.n transmitted at regular time intervals T. The received wave is first conventionally decoded to derive the received symbols therefrom, said symbols are the subjected to a bulk delay which has been determined for shifting the listener echo impulse response to the time reference origin. The delayed symbols are then processed to generate an echo replica which replica is then fedback to the decoder input for being subtracted therefrom.

Abstract: A monolithic module acting as the interface between a modem and leased ("LL") or switched ("SL") telephone lines, mainly characterized in that: 1. It can be formed on a silicon chip (due to the absence of electromechanical relays or similar switching means), and 2. Its architecture is such that it makes it possible, by interconnecting or "stacking" identical modules, not only to attach additional telephone lines, but also to increase the number of allowable modem configurations. The module (10, 10') comprises two controlled-type line amplifiers (DLL, DSL) which exhibit a high output impedance regardless of whether the power supplies are "on" or "off"; two controlled-type line receivers (RSL, RLL) which provide a very high input impedance whether the power supplies are "on" or "off"; and a wrap receiver (WRP) for testing the modem (to the exclusion of the telephone lines) and interconnecting or "stacking" identical modules.

Abstract: A buffer device for a digital transmission network transmitting voice signals, by packets, including so-called purging means for eliminating a number x.sub.(t) of the oldest packets stored in the buffer to prevent saturation thereof. The number of packets received at the input of the buffer within a given time interval is used to address a storage that supplies two pre-stored digital values, namely, x.sub.(t) and L.sub.(t). When the contents of the buffer are equal to L.sub.(t), a number x.sub.(t) of the oldest packets contained in the buffer are dropped.

Abstract: A method and apparatus are disclosed which, for obtaining the quotient of division operations in a data processing apparatus, generate as an auxiliary value the inverse square root g of the divisor w. The auxiliary value g is then multiplied by the divident v, and the intermediate result again multiplied by the auxiliary value g. An improvement in operation of the data processing apparatus is obtained despite introduction of the auxiliary value because the range covered by the auxiliary value is significantly smaller than that of the direct inverse of the divisor. A preferred application is the area of signal processing in communications.

Abstract: The purpose of the receiver is to indicate the reception of a multifrequency signal and to identify said signal. A multifrequency signal is a signal combining two predetermined pure tones, one belonging to a high-frequency range, the other to a low-frequency range. The received signal is sampled at 8 KHz and digitally converted. The signal provided by the converter is simultaneously processed by two tone detectors. Each tone detector comprises: a bandpass filter covering the high- or low-frequency range and supplying the components (x, y) of the filtered signal in Cartesian coordinates; decimation means at the output of said filters; a converter converting the Cartesian coordinates (x, y) into polar coordinates (.rho., .theta.); and logic circuits analyzing the variations of said .rho. and .theta. over fixed periods of time to derive therefrom an identification of the received tone.

Abstract: A multipoint connection system adapted to operate in the time-division multiplex mode. The system includes an output link (21), connected to the output of a control station (10) and to the input of each of the work stations (WS-1, WS-2), and a U-shaped input link (22) one leg of which has its end connected to the input of the control station and the other leg (22-2) of which is terminated by an impedance (Z2) and is connected to the output of each work station. The signals on the output link and on leg (22-2) travel in the same direction, thereby eliminating the need to provide adjustable means of determining the transmission times specific to each work station.

Abstract: A method of initializing a filter in an echo canceller as used in a telephone system that includes hybrid transformers for connecting unidirectional lines to bidirectional lines and vice versa. Said method includes the steps of successively transmitting sequences of real and imaginary components of a signal exhibiting an uniform amplitude (i.e. flat) spectrum; receiving and storing sequences of echoes of each of said sequences of components; calculating the fast Fourier transform of complex sequences obtained from the stored sequences of echoes; rotating the terms of the Fourier transform; calculating the inverse transform of the sequence obtained by rotating said terms; and sorting the terms of the inverse transform to derive therefrom the values of the initial coefficients of said filter in said echo canceller.

Abstract: Information exchange method in a communications controller comprising a central control unit (CCU) associated with a storage that provides a number of parameter/status and data areas equal to the maximum number of interfaces to be managed by the controller. The storage contains a line vector table which indicates the address of each area assigned to each interface. The exchange of the parameter/status information and data on the input/output bus (IO5) uses a minimum number of input/output operations controlled by the program stored in the storage (3).

Abstract: In a TASI system using dynamic subband allocation and BCPCM (Block Companded PCM), losses due to freeze-out or delay are avoided by use of a multi-rate macro-frame format, wherein switching to a lower rate (24, 16, or 8 Kbs) for one or more of the input channels is accommodated by simply dropping one or more sections of each signal frame, since the lower rate bits are distributed over the entire frame.

Abstract: In a computer network a communication session established between a user node such as a data terminal (31) and an application program (13) in a host processor (1) node defines the communication rules to be used and can be shared by a third user node (32, 175) without a new session establishment operation. Session identifier information (138, 158) is stored in the host processor (1) and in a communication controller (2) when a session is established and this stored information is compared with session shareable fields in information units sent from the session sharing third user node (32, 175) to the application program (13a) in the host processor (1). When the session is established between a primary port (161-163) of the communication controller (2) and an application program (13) in the host, it can be shared on transaction basis by a plurality of data terminals (31-33) in a group (3) of terminals operating as secondary ports (171-173) in the network.

Abstract: A communication system comprises several transmission bus segments (A . . . G) to which data stations (ST) are attached. Node units (1 . . . 7) are provided for interconnecting the bus segments which are selectively activated in a predetermined sequence for authorizing message transmission by attached data stations according to any given access protocol. Thus, only small groups of stations contend for access, but all messages are distributed over the whole network. Activation of a bus segment is effected by an authorization message from an assigned node unit. A token message is used to pass the status enabling a node to activate its assigned bus segment, sequentially through all nodes of the network. Each node unit comprises a control unit (17) for sending and receiving token messages and segment activation messages, and further comprises unidirectional amplifier means and switches (11) for establishing a connection between two associated bus segments selectively in either direction.

Abstract: A device for detecting the presence of an alarm tone of a given frequency within a received signal carrying digital data in addition to said tone. The receiver comprises an analog-to-digital converter (42) the output of which is applied to a first recursive bandpass filter centered at the frequency of the alarm tone and the feedback loop of which includes a limiter. In addition, an input feedforward loop is provided for adding (at 58) the output signal from the converter (42), as multiplied by a coefficient .gamma., to the output signal from the limiter. The output signal from the adder (58) is hard limited (at 44), then passed through a second bandpass filter. The energy of the signal obtained at the output of said second filter is then measured to provide indication of a tone's being received when said energy exceeds a predetermined threshold.

Abstract: A circuit for supplying direct current to a line (a, b) from a battery via two supply resistors (RA, RB). Part of the current supplied by the battery flows in a secondary path including a resistor (R4) and a transistor (16), and is maintained at a constant value. A symmetrical and differential resistance bridge connected between the supply resistors and the line detects the transverse alternating current flowing into the battery, and means (15) are provided to cause the transistor to generate a negative-feedback alternating current whose value is adjusted to cancel said transverse alternating current.

Abstract: In the modem based data transmission system the transmitting section provides a bit from each terminal (DTE) to be stored into a transmission buffer register (BX) under the control of an external clock signal derived from a modem internal transmission clock signal. The contents of the transmission buffer register is transferred into a transmission shift register and then transferred toward the modem through a formatting logic circuit wherein so-called stuffing bits and synchronization or flag characters are being inserted. Opposite operations are performed in the receiving section of the data transmission system.

Abstract: This analog-to-digital converter includes a comparator (20) to which the samples X.sub.(n) of the signal to be converted, are applied. The output of the comparator controls a logic circuit (22) producing (N+1) bits to a digital-to-analog converter (24) the output of which is fed back to the input of comparator (20). The converter carries out a converting procedure through N successive approximation steps at the end of which the N most significant bits available at the output of the logic circuit (22) stand directly for the rounded-off digital value of sample X.sub.(n).

Abstract: This invention relates to a process for automatically allocating appropriate communication rates to different data communication lines connected to a common multiplex channel, in terms of the traffic on these lines and the available maximum rate S on this channel, so as to improve the data throughput on the common channel. To this end, Traffic T.sub.i.sup.n is, first, valuated on each line at time t.sub.n, according to formula: T.sub.i.sup.n =.beta.F.sub.i.sup.n +(1-.beta.)T.sub.i.sup.n-1In this formula:T.sub.i.sup.n-1 is the traffic valuation at time t.sub.n-1,.beta. is a coefficient within 0 and 1,F.sub.i.sup.n is given by formula:F.sub.i.sup.n =b.sub.i.sup.n [.alpha.+(1-.alpha.)V.sub.M /V.sub.i ]whereinb.sub.i.sup.n is the number of the bits "0" transferred on to the considered line between times t.sub.n-1 and t.sub.n,.alpha. is a coefficient within 0 and 1,V.sub.M is the highest operating rate on the line, andV.sub.i is the actual rate on the considered line.Once the traffic T.sub.i.sup.

Abstract: In a data processing equipment handling communication lines connected to a central control unit through adapters and a CCU input/output bus, an error reporting device is provided in each adapter for reporting error conditions occurring in the adapter to the central control unit. The adapters are of the type including a microcode controlled microprocessor provided with input and output buses connected to the CCU input/output bus through an interface. The error reporting device in association with dedicated circuits in the interface insures the transmission of the error conditions occurring in the adapter to the central control unit, even when such error conditions affect the integrity of the microcode.

Abstract: The contents of input time-division channels on a closed-loop link (10LO, 10HI) are stored in a memory (173) at the address supplied by an input address counter (IAC) controlled by an incoming timing signal (2MCR). The memory is read out under control of an output address counter (OAC) controlled by an outgoing timing signal (2MCT). Each time interval is divided into one read period and two write periods. Means (186) are provided to select one of the two write periods dependent on the phase relationship between the incoming and outgoing timing signals. The units connected in series by means of the closed-loop link receive a timing signal circulating on a timing loop (15) that is closed by a master timing device (13). Slave timing devices (18) inserted in the timing loop regenerate the timing signals circulating thereon and check same.

Abstract: In the transmitting chip, the bits are serialized and applied to a coding circuit in which bit stream (D) and its complement (D) are transformed into two signals (PH1 and PH2) under the control of a saw-tooth clock signal CK'. Signals (PH1 and PH2) are sent to the receiving chip, wherein they are applied to a decoding circuit which generates two signals (DJ) and (DK) representative of the data bits and a recovered clock signal CLK. The three signals (DJ, DK and CLK) as well as a frame signal (F) are used by a converting and demultiplexing circuit for assembling bytes of parallel data bits.