Abstract: Apparatus and method are provided for segmenting, parsing, interpreting and formatting the content of instructions such as air traffic control instructions. Output from a speech recognizer is so processed to produce such instructions in a structured format such as for input to other software. There are two main components: an instruction segmenter and a robust parser. In the instruction segmenter, the recognized text produced by the speech recognizer is segmented into independent instructions and each instruction is processed. The instruction segmenter receives a recognized air traffic control or other instruction, and segments it into individual commands. Utterances or other language are thereby broken up into their component instructions by detecting probable instruction boundaries. If normal processing fails, then robust backup processing is invoked, as a fallback after a fixed time per word has elapsed or a processing failure has occurred.

Abstract: Modular fascia cover assemblies for rack mounted equipment are disclosed. In a system comprised of several pieces of equipment mounted in a standardized rack, vertical spaces typically exist between the components. These spaces can be filled with fascia cover assemblies, and the present invention provides a modular system that permits openings of nearly any width to be filled. The fascia cover assembly is created by choosing a combination from a few standardized modular parts. The fascia cover assemblies disclosed preferably include components such as an operator panel and pull bar that can be included, respectively, at the top and bottom of the assembly. Most preferably, the operator panel is one and one-half units high and the pull bar is one-half unit high. A cover panel that is one unit high is also included. In certain embodiments, a larger cover panel component is also provided that is three units high.

Abstract: A lead-in guide and starting locator for use with a sheet metal card guide or similar structure is disclosed. The disclosed lead-in guide is preferably of a one piece construction and is most preferably molded or machined from a plastic material. The lead-in guide of the present invention provides multiple board lead-in slots and preferably includes integral retention pegs for quick mechanical attachment or can be held in place by a separate fastener. In a preferred embodiment, the lead-in guide has a top surface cut by a series of grooves that will be aligned with the slots in the card guide. Preferably, the lead-in guide has a front section that is somewhat thicker than the rest of the lead-in guide.

Abstract: An integrated voice and data messaging system is disclosed. The system includes a Server comprising a first computer, a network applications platform (NAP) running on the first computer, and means for storing voice and data messages. In addition, the system includes a Client comprising a second computer with an associated display and means for transmitting analog voice messages and digital data messages to the Server, a Client/Server interface coupling the Client to the Server and providing a medium over which the Client and Server communicate; and a Universal Mailbox Application running on the Server, the Client, or both the Server and Client. The system is capable of visually indicating to a user, via the display device associated with the Client computer, that a message has been delivered for the user and is being held by the Server, wherein the message may be a voice, data or facsimile message.

Abstract: A method and system for optimizing shift operations by reducing the computational overhead and the number of full scan path shifts associated with accessing and modifying data on a rotating scan path image are disclosed. The system further simplifies the construction of a scan path image by inserting a programmable number of leading and trailing bits around a selected string of data bits. The system manipulates and constructs a scan path image without having to shift or prepare the entire scan path image in memory. Specifically, the system comprises a master controller having a lead bypass module, a trail bypass module, a first shift module, a second shift module, a select module and a shift control module. Collectively, these modules comprise the necessary hardware for executing a plurality of shift optimization functions which include lead and trail bypass insertion, non-destructive read, field isolation, field insertion, bit order reversion, bit rotation and simultaneous read and write operation.

Abstract: Microcode is loaded into, for example, a processor or I/O module within a computer system without manually halting and restarting the computer system. In other words, microcode can be loaded into the computer system dynamically while data processing continues from the processor or I/O module states just prior to the microcode load with no major interruption to the user. A microcode image is loaded into a processor which is already executing one or more tasks. A request to load microcode into the processor is received. The processor is signalled to suspend task execution. After the microcode image is transferred into the processor, the processor is signalled to resume task execution.

Abstract: A set of independent pseudonoise (PN) component codes greater than two are combined in a manner which produces one or more I and Q uncorrelated orthogonal pairs of resulting combined PN sequences. At least two of the component codes in a resulting combined PN sequence are combined in a manner which produces an overall imbalance of ones and zeros in the binary expression of the resulting combined PN sequence so that the resulting composite code has a partial correlation with a predetermined one of the PN component codes. In the preferred embodiment, three component codes are combined to produce uncorrelated orthogonal pairs of composite codes wherein at least one of the pairs of composite codes is produced to have a partial correlation with one or more of the component codes.

Abstract: Disclosed is a Significant Bit Calculator (SBC) for determining the number of significant bits or nibbles of an operand in one clock period, and for using the result in performing binary arithmetic operations, such as multiplication and division. By determining the exact size of the operand in one clock cycle, the time spent on processing leading zeros is eliminated. The SBC can be implemented with combinational logic circuitry to compute the number of significant bits or nibbles in a single clock cycle regardless of the number of leading zeros and without any firmware or counter. The time saved using the SBC is proportional to the size of the operand.

Abstract: Apparatus and method that incorporate bussed test access port interface into a system control interface for testing and controlling system logic boards in a manner that is fully compliant with the IEEE 1149.1 standard, while conserving system controller card signals. The apparatus incorporates six signals per interface, which includes the five standard signals as defined by IEEE 1149.1 standard plus a maintenance enable (ME) signal. Four of the standard signals, TCK, TMS, TDI and TRST* are bussed among multiple system logic boards, while the ME signals and the TDO signals are connected in a point-to-point manner between the system controller card and system logic boards. Instruction and data on the TCK, TMS, TDI, and TRST* signals are simultaneously bussed to all system logic boards. These four signals are received by each system logic board through an interface enable circuit, controlled by the ME signal line.

Abstract: An add-on heat sink for increasing the thermal efficiency of an existing heat sink comprises a support base, a first plurality of fins extending from the support base for dissipating heat and a second plurality of spaced fins extending from the support base that are arranged to intermesh with the fins of the existing heat sink and to form an interference fit therewith, whereby the add-on heat sink can be removably attached to the existing heat sink.