Abstract: A latch circuit possesses a scan capability, has a single clock input line, and possesses a locking feature whereby input data, once locked in the latch, is insensitive to further changes in state of the input data. The latch also possesses a novel selection apparatus which functions to select either a scan data input line or a system data input line in accordance with the binary state of a system gate input line, the selection apparatus developing an output signal, the binary state of which is locked in the latch in response to a predetermined state of a clock pulse conducted via the single clock line. Clock skew compensation is provided via the locking feature. During a scan mode, clock skew compensation is provided when the clock pulse is received for a period of time after termination of reception of a scan pulse conducted via the system gate input line.

Abstract: A novel memory system is disclosed which utilizes pipelining techniques to read data from a memory array and to write data to a memory array. More data may be read from the novel memory system, within a unit of time, relative to the amount of data which may be read from a conventional memory system during the unit of time. The novel memory system comprises a plurality of standard elements which include a memory array, including a plurality of rows and columns, a row decoder, a row driver, column sense amplifiers, and a column multiplexer. However, the novel memory system further includes latch circuits interposed between the row decoder and the row driver, between the row driver and the memory array, between the memory array and the column sense amplifiers, and between the column sense amplifiers and the column multiplexer. The same number of latch circuits are interposed in serial fashion between the incoming row and column address bus and the column multiplexer.

Abstract: A method for compensating for video image distortion on a cathode ray tube (CRT) is accomplished by determining the distortion occurring along one axis of deflection of the CRT electron beam. The distortion is determined by predicting the position of the electron beam during a particular scan along the axis of deflection. The rate at which video image information is displayed (pixel rate) via the electron beam is varied according to the predicted position of the electron beam during the scan along the axis.

Abstract: In the processing of instructions in data processing systems it is not always possible to execute these instructions without interruption since particular situations, in the following called events can occur which necessitate a short interruption for executing the operations caused by such events before continuing the interrupted instruction processing. Such repetition however is only possible when the contents of the operation register containing the instruction is frozen during the interruption. Such a situation requires two actions: the first is the execution of a forced operation to resolve the event. The second action is a repetition of the instruction and execution phase of the interrupted instruction.

Abstract: An apparatus is disclosed which detects the existence of an error, in a computer system, corrects the error, and takes steps to ensure that the error will never again re-occur. The error resides in the integrity of data stored in a main memory. When the data is read from memory and found to be erroneous, the data is corrected and stored in a spare portion of a small alternate memory array. In addition, the identity of the corrected data is also stored in the alternate memory array. During a subsequent read of the data from the main memory, the alternate memory array is simultaneously consulted. The identity of the corrected data, stored in the alternate memory array, is compared with the incoming address, and the corrected data is read from the spare portion of the alternate memory array. As a result, the erroneous data is not reproduced during a subsequent read of the data from the main memory.

Abstract: A dual stream processor apparatus, for use in a multiprocessor computer system, is disclosed. The multiprocessor computer system includes at least a first processor and a second processor. A first apparatus and a second apparatus is included in both the first processor and the second processor for use when either the first or the second processor is inoperative. The first apparatus, disposed within the inoperative processor, suspends the functional operation of the inoperative processor. The second apparatus, disposed within the inoperative processor, transmits a miss signal to the other remaining functionally operational processor. When the other remaining processor receives the miss signal, it will not subsequently attempt to locate desired data in the cache of the inoperative processor. Rather, the other remaining processor will search for the desired data in the main memory in the event it cannot locate the data in its own cache.

Abstract: A bypass apparatus in a computer system is disclosed. The computer system includes a central storage facility for storing various instructions to be executed, an instruction register for storing an instruction being executed, and an instruction buffer, interconnected between the central storage facility and the instruction register, for temporarily storing the next instructions to be executed following execution of the instruction stored in the instruction register. A bypass path interconnects the central storage facility directly to the instruction register for bypassing the instruction buffer when certain special instructions being held in the instruction register are being executed, such as an EXECUTE instruction. Consequently, the contents of the instruction buffer are not lost or destroyed as a result of execution of the special instruction.

Abstract: Bus command generation apparatus is provided for a microprocessor implemented data processing system that uses a multibyte width system bus requiring a bus command byte since a complete bus command byte is ordinarily unavailable directly from a microprocessor. A bus command register is loaded with a preliminary bus command, certain bits of which are then modified in accordance with the operation to be performed. The limited command information available from the microprocessor that controls I/O operations is utilized to modify the preliminary bus command bytes without any need to access memory for bus command information. The bus command generation apparatus is adapted to pass a preliminary bus command byte unaltered, under predefined conditions, to the system bus.

Abstract: In a computer system, an instruction is executed. The results of the execution of the instruction are stored, and, simultaneously with the execution of the instruction, information is generated and stored which is related to the results of the execution of the instruction. This information is used by the computer system during the execution of subsequent instructions. The results of the execution of the instruction comprise a binary number. The information which is generated, simultaneously with the execution of the instruction, includes, inter-alia, a count of the number of binary "1" bits and binary "0" bits which constitute the binary number, and a set of addresses representing the address locations of each bit of the binary number which constitutes the stored results of the execution of the instruction.

Abstract: Synchronization of peripheral operation with that of a processor in a multi-microprocessor implemented data processing system is achieved by bus cycle alteration. A logic circuit is provided for monitoring the condition of a peripheral's status bits and for preventing an appropriate processor control signal from completing the present bus cycle if the peripheral of interest is not able to accept an access. The peripheral of interest is readily identified by providing unique memory mapped locations, one for each system peripheral, that are responsively connected to the logic circuit.

Abstract: A direct module powering scheme is disclosed. A plurality of integrated circuit chips are mounted on a module. The module is mounted on a printed circuit board. A plurality of metallization layers are distributed in parallel fashion within the module. A voltage tab is mounted on the edge of the module substrate and in contact with the edge of the metallization layers. The voltage tab may be attached to a source of power for providing the necessary voltage and current to the module needed to power the chips mounted on the module. The metallization layers comprise voltage distribution layers and voltage reference (ground) layers. The voltage tab is connected to the edge of the voltage distribution layer. A plurality of plated vias are disposed through the module in contact with one or more of the metallization layers.

Abstract: A compression and a decompression algorithm resides in a memory of a data processing system. The data processing system communicates to another data processing system via an input/output means and a telecommunications network. When a message, to be communicated to the other data processing system, is ready for transmission, the data processing system compresses the message data. A processor of the data processing system compresses the data using the compression algorithm stored in the memory of the data processing system.

Abstract: The detailed testing of processors, manufactured according to very large scale integration principles, which also extends to secondary functions of operations, such as the setting or non-setting of particular state indicators, necessitates the transfer of large quantities of test data between the processor and the tester, for which purpose no distinction is drawn between external and integrated testers. For testing such structures, the known LSSD method is frequently used wherein the storage elements of the logic subsystems are combined in the form of shift register chains for testing. To permit a fast exchange of test data on the system bus, connecting the processor to a tester, interface register stages are also included in the shift register chain which has a garland-shaped structure and whose beginning and end are connected by a controllable switch during testing.

Abstract: An apparatus disposed within a computer system is disclosed for sensing the existence of an error occurring within a computer system and for suspending an internal system clock when a certain number of clock pulses are generated following the occurrence of the error. When the internal system clock is suspended, operation of the computer system stops. In the preferred embodiment, the internal system clock is suspended when two (2) clock pulses are generated following the occurrence of the error. As a result, it is not necessary to wait until execution of the current instruction is complete before stopping the operation of the computer system. Therefore, other errors are not generated within the computer system as a result of the generation of the initial error.

Abstract: An on-chip clock signal generator circuit is disclosed. The clock signal generator generates a high frequency clock signal in response to a system clock developed from a source located at a point external to the chip. The clock generator circuit includes an apparatus for stabilizing the frequency of the clock signal generated by the clock signal generator, this apparatus stabilizing the frequency of the clock signal by minimizing the variation in the position of the intermediate pulses which comprise the clock signal.

Abstract: In a computer system, an apparatus detects the existence of an error in data retrieved from memory, corrects the erroneous data, and takes steps to maintain the correct condition of the data. In taking these steps, when the erroneous data is corrected, the corrected data is stored in a spare portion of the memory; however, the address of the corrected data in memory is recorded in a bit steering array, a physically separate memory of much smaller size. The bit steering array stores a plurality of such addresses. When an incoming read request signal is generated, it simultaneously energizes the memory and the bit steering array. In response to the read request signal, the bit steering array develops an output signal indicative of the address of the corrected data and representative of the identity of the erroneous data. In response to the read request signal, data, including the erroneous data, is read from memory. In addition, the corrected data is read from the spare portion of the memory.

Abstract: A graphics display terminal is disclosed having a capability of responding to at least two unique input commands. A first assigns a segment to a group of classes and also removes the segment from membership in another group of classes. A second is a matching condition which requests that all the segments lying within a certain group of classes and/or not lying within another group of classes be identified, the CRT terminal highlighting these identified segments in response to a command from the operator. The second command is called a matching condition. Once all of the segments in a memory are located, which satisfy the matching condition, the operator can direct the terminal to blink or otherwise highlight the identified segments retrieved from memory.

Abstract: The performance of a multimicroprocessor implemented data processing system that emulates a mainframe is enhanced by providing a pair of override latches that serve to steer accesses between main and control storage for instruction fetch and operand acquisition in a manner that minimizes the complexity and size of microprocessor interface microcoding. This is achieved by connecting the instruction and operand override latches between a primary microprocessor, a secondary microprocessor, off-chip control storage belonging to the secondary microprocessor, particularly memory mapped private storage therein, and main storage. The override latches are made responsive, via microcode provided for that purpose, to the type and cause of each memory access. The override latches are set or reset by a memory mapped write to a predefined address in the secondary control store after being enabled by control lines responsive to the particular microprocessor action being taken.

Abstract: A failure detection apparatus detects the existence of an abnormal circuit condition in a circuit which causes a subsequently transmitted data byte to be transmitted from one integrated circuit to another integrated circuit out of sequence relative to a previously transmitted data byte. Even and odd data bytes are received by the first integrated circuit with odd parity. However, the even data byte is transmitted from the first integrated circuit to the second integrated circuit, along existing interface lines extending between the integrated circuits, with odd parity. The parity bit of the odd data byte is inverted, the odd data byte being transmitted along the existing interface lines with even parity.

Abstract: An apparatus for time aligning data acquired by one test instrument with corresponding data acquired by another test instrument is disclosed. A set of binary codes, representative of a set of instructions executed by a microprocessor disposed within a user's prototype circuit, are acquired by said one test instrument. With the acquisition of each of said binary codes, a count is developed in a counter indicative of each said acquisition. A multitude of binary data is acquired, independently of the acquisition of the set of binary codes, by said another test instrument, the multitude of binary data being representative of the functions performed by a set of components present within said user's prototype circuit. The binary codes acquired by said one test instrument and the binary data acquired by said another test instrument each have associated therewith a count developed from said counter.