Abstract: A special purpose pulse amplifier with programmable high and low levels for complex IC testing is disclosed. Its output has independently programmable positive and negative transition rates and is reverse terminated in 50 ohms. It also has the ability to be switched to a high resistance, low capacitance output state. This circuit is the interface between a complex, computer controlled system of timing and pattern generation hardware, and an integrated circuit to be tested. This device has reduced waveform aberrations, lower inhibited capacitance, low input to output delay for reducing timing error, programmable signal transition rates, and the amplitude range and transition rate control to accommodate all the important device technologies expected in high pin-count parts.

Abstract: An image quality enhancement scheme is disclosed wherein the image information associated with each line of an image source is transferred to one line of an image receiving medium a plurality of times, the quality of the image information transferred to one line of the image receiving medium gradually improving following each subsequent transfer. A fiber optic cathode ray tube (CRT) transfers the image information to the image receiving medium. An electron beam generator in the CRT traces a plurality of scan lines on the inner faceplate of the CRT. The image receiving medium scrolls across the face of the CRT in synchronism with the trace of each of the scan lines on the inner faceplate thereof. The image information associated with each line of the image source is transferred to the one line of the image receiving medium via the trace of each of the plurality of scan lines.

Abstract: A method and apparatus for establishing the correct order of probe channels in a logic analyzer is disclosed. Logic analyzers have probe PODS connected thereto, the PODS having a plurality of probe tips connected thereto for further connection to the terminals of a product under test. With this invention, the order of connection of the tips to the terminals can be ignored because the correct order is established via the logic analyzer (LA) itself. A ROM has firmware stored therein for enabling the logic analyzer to establish the correct order of connection. The binary data from each POD is stored in memory. The binary data in memory may be converted to hexadecimal form and stored in the display controller. By using a keyboard, the operator displays, on the LA display, a menu-mode display, which includes a display of the probe channel identifiers for each POD, the identifiers reflecting the actual order of connection of the probe tips to the terminals of the product under test.

Abstract: A cache memory for a data processing system having a tag array in which each tag word represents a predetermined plurality or block group of consecutively addressable data block locations in a data array. The lower order set address bits concurrently access the tag word and its associated group of block locations in the data array while individual blocks within the group are accessed by supplemental block bits. Each tag word read out must compare equal with the high order bits of the address and an accompanying validity bit for each block location in its group must be set in order to effect a hit. Also described are circuits for writing into the cache and adapting the cache to a multi-cache arrangement.

Abstract: An input apparatus for a logic analyzer is disclosed which receives a plurality of logic signals from a probe, the plurality of logic signals being received at different points in time, the input apparatus being capable of generating a corresponding plurality of logic signals in response thereto, the time of generation of the corresponding plurality of logic signals substantially coinciding with the time of generation of a corresponding reference logic signal. The input apparatus comprises a plurality of tapped delay lines corresponding to the plurality of received logic signals. A controller controls the amount of time delay for each delay line associated with each received logic signal. The controller continues this control function until the time of generation of the corresponding plurality of logic signals substantially coincides with the time of generation of the corresponding reference logic signal.

Abstract: A zero insertion force connector and printed circuit card retention and polarization arrangement wherein the card has circuit tabs along one edge and the connector has spring contacts which engage the tabs with a wiping action when they are closed. A pin is provided at one end of the connector and a pin slot at the opposite end. A pin slot is provided at one end of the card and a pin at the opposite end, the pin and pin slot in the connector and pin slot and pin in the card being arranged to respectively come into engagement when the card is inserted into the connector to prevent movement of the card when the connector spring contacts are closed.

Abstract: An apparatus of providing vertical smoothing of convergence correction signals in a digital convergence system is disclosed. The surface of a cathode ray tube is subdivided into a matrix including a plurality of intersecting rows and columns and having a plurality of intersections corresponding thereto. A value is assigned to each intersection of a row and a column of said matrix. An electron beam traces a plurality of scan lines within each of the rows of the matrix. For each scan line within a row of the matrix, a convergence correction signal is synthesized using the plurality of values associated with the plurality of intersections in said row. A plurality of horizontal discontinuities are present in the convergence correction signal as a result of the different magnitudes associated with the plurality of values used to synthesize the convergence correction signal.

Abstract: A system and method for receiving an input bit stream defining a non-interlaced video image and for producing concurrently an output bit stream defining an interlaced representation of such image. Intermediate storage of every other input raster line in a first-in/first-out oriented memory permits the output of the interlaced signal to be interleaved with the receipt of the non-interlaced input, and the interleaving of the input and output operations permits the use of a memory module having a capacity less than that required to store a complete raster line of input information. Provision is also made for synchronizing the output operation to U.S. or European standards.

Abstract: A substantially transparent interference shield wherein a flexible material employed to form an interlayer laminating a thin metal screen between two panels of glass is extended beyond the periphery of the panels a distance less than the screen so as to provide the necessary support permitting the shield to be mounted in a surrounding frame solely by clamping engagement of the extended screen. Provision is also made for the additional encapsulation within the flexible material of a resilient gasket employed to enhance electrical contact between the screen and the frame.

Abstract: Electrographic paper is fed over a segmented platen where its dielectric surface receives image defining electrostatic charges deposited by styli bearing directly and successively upon it. The styli are integral to an endless belt moving laterally to the surface. Voltage pulses corresponding to the input information are applied to the segmented platen to produce the electrostatic charges. The latent image charged surface is progressively fed to an image toning and fixing cycle to produce a hard copy.