Abstract: A circuit for optimizing the transmission of data on a communication channel is disclosed. According to one embodiment of the invention, a circuit comprises a transmitter circuit having a programmable output characteristic and being coupled to a transmission media. The transmission media receives serial data from the transmitter circuit and couples the data to a receiver circuit by way of the transmission media. A signal quality monitor associated with the receiver circuit generates received signal quality data. Finally, a feedback path couples the received signal quality data to the transmitter circuit.

Abstract: A circuit for enabling reading data in an asynchronous FIFO memory of an integrated circuit is described. The circuit comprises a memory storing data in a plurality of slots having a corresponding plurality of addresses. A write address counter stores a write address count, while a read address counter stores a read address count. Finally, a backup circuit receives a read address associated with data read from a slot of the plurality of slots. According to an alternate embodiment, a most significant bit circuit is coupled to an output of the write address counter for setting the most significant bit of the write address. A method of reading data stored in an asynchronous FIFO memory of an integrated circuit is also disclosed.

Abstract: Circuits and methods of rearranging the order of data in a memory having asymmetric input and output ports are disclosed. According to one embodiment, a method comprises steps of providing an input port of a memory having an input width and output port having an output width which is different than the input width. A plurality of data words are received at the input of the memory, wherein each data word has a width corresponding to the input width. The order of the plurality of input data words is rearranged; and an output word based upon the rearranged data words and having a width corresponding to the output width is generated. Various circuits and algorithms for implementing the methods are also disclosed.

Abstract: Various embodiments of the present invention describe circuits for and methods of detecting a defect in a component formed in a substrate of an integrated circuit. According to one embodiment, a circuit comprises a plurality of components formed in a substrate and coupled in series by a plurality of signal paths extending from a first end to a second end. An input signal coupled to the first end of the first signal path is detected a signal detector coupled to a second end of the first signal path to determine whether there is a defect in a component formed in the substrate. Switching networks at the inputs and the outputs of the plurality signal paths enable determining a particular signal path that had a defect. Alternate embodiments describe circuits for determining the location of a defective component in a signal path. Various methods of detecting defective components are also described.

Abstract: A lid having a plurality of recesses at the edges of the lid to provide an improved adhesive bond between the lid and a substrate of an integrated circuit is disclosed. The plurality of recesses may be a castellation comprising a collection of semi-circular cuts into the originally straight edges of the lid. The castellation can be formed by stamping, etching, molding design, or milling/drilling, all of which are well-known methods in the art of forming lids for integrated circuits. The castellation can be vertically straight or it can be slightly tapered, to provide a better locking of the lid on to the package. Epoxy in the recesses can provide an epoxy post for locking the lid. Method of forming a lid having a plurality of recesses and employing a lid on an integrated circuit are also disclosed.

Abstract: A method of testing circuits in a programmable logic device is described. According to one embodiment of the invention, a method comprises steps of configuring a configurable logic block of the programmable logic device with a test signal source and a logic circuit; routing the test signal source to the logic circuit; and determining if the logic circuit is defective. According to an alternate embodiment, a method enables re-routing a path from a shift register to a lookup table to determine whether a lookup table is defective. According to a further alternate embodiment, a method enables localized routing to reduce the probability that a defect is a result of a routing defect.

Abstract: The various embodiments of the present invention relate to circuit verification. According to one embodiment of the invention, a method of enabling timing verification of a circuit design comprises steps of generating a timing model of a processor core for a static timing analysis tool; coupling timing data related to the processor core to the static timing analysis tool; extracting resistance and capacitance data for interconnect circuits of the circuit design; coupling the resistance and capacitance data for the interconnect circuits to the static timing analysis tool; and verifying the performance of the circuit design using the static timing analysis tool. According to another embodiment of the invention, a system for enabling timing verification of a circuit design is described.

Abstract: A circuit for implementing a plurality of circuits on a programmable logic device, the circuit comprising a first circuit implemented on a first portion of the programmable logic device; a second circuit implemented on a second portion of the programmable logic device; and a control circuit coupled to the first circuit and the second circuit, the control circuit providing isolation between the first circuit and the second circuit. While the first circuit and the second circuit may comprise redundant circuits implementing a common function, the circuits may also comprise circuits which must be isolated, such as an encryption circuit and a decryption circuit implementing a cryptographic function. A method for implementing a plurality of circuits on a programmable logic device is also disclosed.

Abstract: A programmable logic device (PLD) includes a central processing unit (CPU) and a programmable interface coupled to the CPU, wherein the programmable interface includes a core designated by a user. The programmable interface core allows devices, both on and off-chip, to communicate with the CPU. In one embodiment, the programmable interface core includes a crosspoint switch for coupling a plurality of devices and the CPU. Re-programmability of the PLD provides significant flexibility in providing features that can be parameterized based on the user's needs and/or associated design. Specifically, these parameterized features can be implemented in programmable resources on the PLD, thereby allowing these features to be modified at any time. Moreover, only those resources actually needed for the programmable interface core need be implemented, thereby allowing the user to optimize use of the remainder of the PLD.

Abstract: According to one embodiment of the invention, a method of accessing instruction data from a memory comprises steps of specifying a predetermined address of a memory for storing instruction data; writing instruction data to the predetermined address in the memory; reading the instruction data from the predetermined address after the step of writing instruction data; and determining whether the instruction data is valid. According to another embodiment of the invention, a method describes a method of accessing instruction data from a memory by way of first and second data buses. According to a further embodiment, instruction data read back from the memory is multiplexed to a memory controller. A circuit for accessing instruction data written to a memory is also described.

Abstract: A circuit enabling the realignment of data is described. The circuit generally comprises an input multiplexer receiving a first plurality of input data bytes and a second plurality of input data bytes; a switching controller coupled to the input multiplexer and controlling the output of the data bytes from the input multiplexer; a delay register coupled to the input multiplexer and receiving predetermined bytes of the first plurality of input data bytes; and an output multiplexer coupled to the input multiplexer and the delay register. The output multiplexer receives the predetermined bytes of the first plurality of input data bytes and predetermined bytes of the second plurality of input data bytes.

Abstract: An integrated circuit package having a lid is disclosed. The integrated circuit package comprises a substrate having an embedded conductor exposed on a surface; a lid comprising a plurality of conductive portions; and a solder bond between the embedded conductor and the plurality of conductive portions of the lid. The substrate may comprise a recess for receiving a flange associated with the walls. The embedded conductor preferably comprises a conductor coupled to a power or ground plane of the substrate. A standoff within the walls may optionally be soldered to a contact pad on the substrate. A method of assembling an integrated circuit package is also disclosed.

Abstract: A design is used for coordinating channel bonding operations of a set of transceivers. The set include a master transceiver and a plurality of first level slave transceivers that perform channel bonding operations. Each first level transceiver is controlled by the master transceiver. The set also comprises a plurality of second level slave transceivers that perform channel bonding operations. Each second level transceiver is controlled by one of the plurality of first level transceivers. Any transceiver can be set as either a master, a first level slave or a second level slave. The design comprises a plurality of flip-flops and multiplexers, and is controlled by a MODE signal that determines the mode of operation of the design.

Abstract: A client-server semiconductor verification system is described. The system comprises a client device storing a test job having test vectors and configuration data for programmable logic for testing a design of a logic circuit. A server is coupled to the client device and receives the test job from the client device. Finally, a system under test coupled to the server and has programmable logic which is reconfigured. The system under test receives the test vectors and outputs result vectors to the client device by way of the server. Corresponding methods are also disclosed.

Abstract: A circuit for buffering data is disclosed. The circuit comprises a first circuit which is coupled to receive a stream of data blocks using a first clock signal. The first circuit removes data blocks, such as idle data blocks or a sequence ordered set of a pair of consecutive sequence ordered sets, from the stream of data blocks to create a first modified data stream which is coupled to a memory device. Finally, a second circuit coupled to the memory device generates a second modified data stream using a second clock signal. The second modified data stream preferably comprises the data blocks of the first modified data stream and idle data blocks inserted among the data blocks of the first modified data stream. Methods of buffering data received in a first clock domain and output in a second clock domain are also disclosed.

Abstract: According to one aspect of the invention, a circuit for determining the location of a defect in an integrated circuit is described. The circuit comprises a conductor extending from a first node to a second node and a test signal driver coupled to the first node of the conductor. The test signal driver receives a test signal using a first clock signal, while a plurality of detector circuits coupled to the conductor between the first node and the second node to detect an output at the plurality of nodes using a second clock signal. According to other embodiments, circuits for determining the location of a defect in a programmable logic device are disclosed. Finally, various methods for determining the location of a defect in an integrated circuit are described.

Abstract: A fast linked multiprocessor network (22) including a plurality of processing modules (24, 26, 28, 30, 32, and 34) implemented on a field programmable gate array (10) and a plurality of configurable uni-directional links (21, 23, 25, 27, 29, 31) coupled among at least two of the plurality processing modules providing a streaming communication channel between at least two of the plurality of processing modules.

Abstract: A method of verifying a circuit implementing a data transfer protocol is disclosed. According to one embodiment of the invention, the method comprises steps of providing a block under test that implements a variable latency data transfer protocol; coupling a verification circuit to the block under test; enabling variable latency data transfers to the block under test; and verifying that the block under test is implementing the variable latency data transfer protocol. The method could be implemented to verify the operation of a memory controller of an FPGA, for example. According to another embodiment, a method enabling a multi-stage verification is disclosed. Finally, specific implementations of a verification circuit coupled to an on-chip memory controller of an FPGA are disclosed.

Abstract: A method of employing a plurality of integrated circuits in a multi-chip module is described. The method comprises steps of identifying a defective programmable logic device implemented on a first die; identifying a functional programmable logic device implemented on a second die; and coupling the defective programmable logic device and the functional programmable logic device. According to an alternate embodiment, a method of employing a plurality of integrated circuits in a multi-chip module comprises steps of configuring a plurality of programmable logic devices on a multi-chip module. A multi-chip integrated circuit package is also described.

Abstract: The present invention relates generally to integrated circuit trays, and in particular, to an integrated circuit tray enabling communication with integrated circuit stored therein. A storage tray for storing integrated circuits according to one embodiment of the invention comprises a plurality of recesses adapted to receive an integrated circuit. A conductor extends between the plurality of recesses and comprises a plurality of contacts associated with the recesses. A terminal portion, such as a connector, is coupled to the conductor to enable programming the integrated circuits stored in the tray. Embodiments having additional components are also described. Further, embodiments for connecting a plurality of trays and enabling programming of integrated circuits in the plurality of trays are also described. A system for programming integrated circuits in a storage device is also described. Methods of communicating with a plurality of integrated circuits in a storage tray are also disclosed.