Abstract: The present invention provides a planar antenna having a scalable multi-dipole structure for receiving, and transmitting high-frequency signals, including a plurality of opposing layers of conducting strips disposed upon either side of an insulating (dielectric) substrate.

Abstract: A heat exchanger having a set of heat exchanging coils supported in a horizontal direction. The coils operate to exchange heat in fluids provided to the coils from a source device via a supply header tube and returned to the source device (or provided to a second device) via a return tube. A backbone supports the heat exchanging coils. Preferably, the backbone runs inside the heat exchanging coils. A bracket attached to the backbone secures a set of exchange tube supports to which the exchanging coils are attached. The heat exchanger provides a strong structure that is able to withstand currents and tidal action when mounted under a pier or in other aquatic environments. An adjustable riser device provides for flexible installation.

Abstract: A dual mode, substantially planar antenna utilizes a dipole or monopole structure for receiving and transmitting high-frequency signals. Layers of conductive strips are disposed on opposite sides of an insulating (dielectric) substrate, such as printed circuit board material. First and second antenna elements are connected via an LC trap, the first antenna element corresponding to a first mode and the combined elements corresponding to a second mode. The LC trap is a single component inductor with parasitic capacitance sufficient to implement the LC trap or a set of patterns printed on the substrate. In one embodiment, the LC trap is constructed with only a single via through the substrate. The antenna is ideally suited for combined 5.5 GHz and 2.4 GHz RF operations.

Abstract: Symbol timing is performed by providing a histogram of samples of a signal for a predetermined number of symbol times. An average, weighted average, or other method is applied to determine an average timing for a max eye opening for each symbol time. The average max eye opening timing is applied to an edge detection of a currently received signal to determine timing of a sample that is most likely to occur closest to the max eye opening for the current symbol. The invention may also be practiced based on a center timing of each symbol.

Abstract: A dehydrated composition is provided that includes freeze-dried platelets. The platelets are loaded with trehalose which preserves biological properties during freeze-drying and rehydration. The trehalose loading is conducted at a temperature of from greater than about 25° C. to less than about 40° C., most preferably at 37° C., with the loading solution having trehalose in an amount from about 10 mM to about 50 mM. These freeze-dried platelets are substantially shelf-stable and are rehydratable so as to have a normal response to an agonist, for example, thrombin, with virtually all of the platelets participating in clot formation within about three minutes at 37° C.

Abstract: A method and apparatus for critical and false path verification takes all the potential false paths and captures the conditions that would make them true paths (or false paths) as a Boolean expression (net list), for the combinational logic only. The net list does not have to be at the gate level, but can be a simplified gate level representation because the verification process is only concerned with the logical behavior, not the actual structure. This allows the simulation to execute more quickly. Since the conditions are only captured between register elements, it can be formally proved whether or not the path can be exercised. If no register value can activate the path, then the analysis is done. Otherwise, a simulation is performed to determine whether the register values required to active the condition actually occur. If the Boolean condition can be satisfied, the simulation is performed on the sequential logic to justify those values.

Abstract: A method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method, accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk, upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, as a system on a chip, in compliance with the criteria and modified constraints, and substantially without changing the selected circuit block and the processing method.

Abstract: An improved dental mirror for facilitating the accurate visualization and measurement of structures and distances and for facilitating the assessment of parallelism between non-adjacent teeth. The dental mirror includes an elongated handle having a longitudinal axis and affixed to one end thereof is a mirror frame. The mirror frame supports a planar mirror of rectangular geometry having a perimeter defined by a pair of major parallel edges and minor edges. A series of calibrations are provided along the perimeter of the mirror whereby at least one of the edges is calibrated by lines of demarcation. A plurality of angulations between handle axis and major parallel edge, in the plane of the mirror, is achievable by a rotation mechanism or on a series of fixed angle dental mirrors with different orientations.

Abstract: A method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method, accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk, upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, as a system on a chip, in compliance with the criteria and modified constraints, and substantially without changing the selected circuit block and the processing method.

Abstract: A method for timing verification of very large scale integrated circuits reduces required CPU speed and memory usage. The method involves steps including partitioning the circuit into a plurality of blocks and then partitioning the verification between shell path components and core path components. Timing verification is then conducted for only shell path components while core path components are abstracted or ignored. Finally, timing verification for core path components in each block completes the process for the entire design.

Abstract: A feasible floorplan of a circuit is determined and budgeted in the early phases of circuit design. The process of determining the floorplan and budget includes estimating RTL complexity, physical partitioning, block placement, block i/o placement and top level global routing, and verifying feasibility of the floorplan. Allocation of global timing constraints to each block is performed by producing logic cones representing timing of circuit paths in each block. The circuit paths are optimized to determine a feasible timing for each block. The global constraints are allocated proportionally to each block based on the feasible timing for each block.

Abstract: A method and apparatus for synchronizing multiple signals is provided. The method and apparatus utilize the timing information of one of the multiple signals as a reference clock for synchronizing multiple signals. The method and apparatus utilize selectively gating the clocks of the other signal processing chains in order to allow control by the reference clock.

Abstract: A system and method for remote maintenance and service of one or more wireless modems in communication with a wireless hub is provided. The system and method include the capability of the wireless hub to instruct the wireless modem(s) to change any operational parameters in order for the wireless hub to diagnose any problems with or to improve operation of the wireless mode.

Abstract: Wide dynamic range and stability are achieved by adjusting a gain control resistance of an amplifier such that the pole ratio between the input and output is stable and by using a gain compensation technique to adjust output current. Adjustment of the gain is performed by determining a peak voltage between a gain stage and a dummy gain stage amplifier that does not amplify the input voltage. The peak voltage is compared to a gain control reference voltage and the comparison output is used to regulate both the variable gain and the gain compensation. The variable gain is performed using an FET variable resistor in a feed back loop of the amplifier. The gain compensation technique uses an FET variable resistor to adjust a voltage level of a driving transistor that adjusts an amount of current provided to an input of a current mirror. The mirrored current is then used to drain bias current from the amplifier.

Abstract: Described is a method for forming a physical layout on a chip floor for a circuit design based on a netlist. The method tentatively places each of the gates of the netlist to a physical location on the chip floor. The method then estimates potential signal integrity and reliability problems. If the placed net list is not acceptable for not being able to meet the requirements of the circuit design, the method modifies the netlist and re-places each of the gates in the modified netlist into a physical location on the chip floor. The method then re-estimates the potential signal integrity and reliability problems. The method repeats this process until the estimation to the-placed or re-placed netlist is acceptable for being able to meet the requirements of the circuit design.

Abstract: Log entries in a system that produces status or other log data (ASIC verification system, for example) are saved in a circular buffer until a trigger event occurs. Typically, the system operates on a Device Under Test (DUT), but may apply to other systems that simply monitor or gather information. When the trigger occurs, a window of the saved log entries are saved to disk. A level of granularity of the reporting for the log entries is set at any point between low level (cycle based) reporting (recording every event) to high level functional descriptions of the processes or activities performed by the system, DUT, or other item being monitored. Log data from various modules of the system are grouped together to provide a logical view of the recorded log entries.

Abstract: A method and system are disclosed for finding the best match from a target library of simple logic cells for a complex logic circuit conception. The inventive method is flexible and can be adapted to several cost functions or criteria. The inventive method finds the best children nodes for a match of simple gates (AND, OR, NAND, NOR). The method allows one to improve the overall area of the final design while respecting the time constrains. It also allows one to smartly speed up the tiler process as this process does not have to investigate exhaustive lists of possible children. Two preferred embodiments are disclosed. One such embodiment is designed to improve slack time and the other is designed to minimize required area.

Abstract: Spatially diverse signals are simultaneously demodulated and error corrected providing statistically independent data. Statistics for the signals are prepared and available for system management and display to users.

Abstract: A Wireless bridge conjoins two previously incompatible technologies within a single device to leverage the strengths of each. The Wireless bridge marries the Personal Area Network (PAN) technology of Bluetooth as described in Bluetooth Specification Version 1.0B with the Wireless Local Area Network (WLAN) technology described in the IEEE802.11aspecification to provide a wireless system level solution for peripheral devices to provide Internet service interactions. The invention brings together in a single working device implementations of these technologies so they do not interfere or disrupt the operation of each other and instead provide a seamless transition of a Bluetooth connection to Wireless Local Area Network/Internet connection. From the Wireless Local Area Network perspective the inventive wireless bridge extension allows a Bluetooth-enabled device to roam from one Wireless Access Point (bridge) to the next without losing its back end connection.

Abstract: A phone application includes a note button. During a call, when the note button is pressed, a note entry screen is presented to a user. The note entry screen is pre-populated with information already known about the phone call (number of caller, number dialed, name of caller, name of person called, etc.). The know information is retrieved from network data, including phone number and caller id for incoming calls, and the number dialed for outgoing calls, each in conjunction with the user's address book. The user completes the note entry screen including any notes the user wishes to make regarding the phone call. Upon completion of the note, if an address book entry has not been made or is incomplete, an address book entry screen is presented to the user to make or complete an entry for the caller/person called. The phone application runs on a PDA having telephone capabilities.