Patents Represented by Attorney, Agent or Law Firm Jose Gutman
  • Patent number: 8349253
    Abstract: A product package is provided for containing a product or object. The package contains a first agent that is energizably convertible by an energy source to a sanitizing agent including ozone in the package. The sanitizing agent including ozone in the package is transferred to the product or object while in the package. The first agent can include oxygen. The oxygen converts to ozone after being energized by ultraviolet radiation energy inside the package. The ultraviolet radiation energy can be radiated from outside the package, through the package, and into the package to energizably convert the oxygen to ozone in the package. The product or object in the package can be treated with the sanitizing agent including ozone in the package to provide a sanitizing, disinfecting, or sterilizing treatment, in the package.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: January 8, 2013
    Inventor: Jose Gutman
  • Patent number: 7976777
    Abstract: A method, a sensor device (204), and a package storage system (200), are used to monitor the inside of a storage volume in a package container (202) containing at least one product and/or object (201). The sensor device is inside of the storage volume in the package container (202) and senses the presence of at least one of a sanitizing agent comprising ozone (316) and ultraviolet radiation energy inside of the storage volume. The sensor device (204) wirelessly transmits the sensed information from inside the at least one storage volume to a wireless receiver (222) outside of the storage volume to provide the sensed information to a processor (220) that monitors the presence of the at least one of the sanitizing agent comprising ozone (316) and ultraviolet radiation energy inside of the storage volume in the package container (202). The sensor device (204) can communicate using an RF ID device communication protocol.
    Type: Grant
    Filed: September 13, 2005
    Date of Patent: July 12, 2011
    Inventor: Jose Gutman
  • Patent number: 7500586
    Abstract: A hanger is adapted for retaining and hanging objects. The hanger includes a hook having first and second ends, a bead being attached to the second end. The hook defines an upper portion of the hanger. A lower hanger portion includes a spiral-shaped body having first and second ends, the second end being free to accept objects for hanging on the lower hanger portion. The first end of the lower hanger portion is coiled around the second end of the hook upper portion of the hanger.
    Type: Grant
    Filed: December 1, 2005
    Date of Patent: March 10, 2009
    Assignee: Danver LLC
    Inventor: Julia Oliveira-Martinez
  • Patent number: 6942834
    Abstract: A method and packaging system receive products and/or objects in a packaging storage volume, the packaging storage volume contains a first agent including oxygen that is energizably convertible by an ultraviolet radiation energy source to a sanitizing agent including ozone in the packaging storage volume, the sanitizing agent including ozone being transferable to the products and/or objects to provide at least one of a sanitizing, disinfecting, and sterilizing, application to the products and/or objects. The system also includes at least one of an incline, a ridged surface, ridged strip, a baffle structure, and other structure for providing rotational motion to the products and/or objects being stored in the packaging storage volume for exposing surfaces of the products and/or objects to the sanitizing agent comprising ozone and to the ultraviolet radiation energy. Additionally, a packaging storage control system is provided with timed intervals for exposure to sanitizing applications.
    Type: Grant
    Filed: June 10, 2002
    Date of Patent: September 13, 2005
    Inventor: Jose Gutman
  • Patent number: 6825551
    Abstract: A method of producing a package (30) for a semiconductor die (or chip) including a semiconductor die (20) having one or more bond pads on the top surface for providing terminals for one or more sensors (22) in the upper surface and a die carrier (32) including an opening (34) and one or more external terminals. The semiconductor die (20) upper surface is fixed on the die carrier (32) and each bond pad is coupled to a portion of the external terminals exposed at the die carrier (32) lower surface, for example, with weld points (42). A sealing ring (44,46) encapsulates the interface zone (40) and a coating material (48) encapsulates the die carrier (32) lower surface and a lower surface of the semiconductor die (20).
    Type: Grant
    Filed: July 1, 2002
    Date of Patent: November 30, 2004
    Assignee: STMicroelectronics S.A.
    Inventor: Antonio Do Bento Vieira
  • Patent number: 6817000
    Abstract: A method and system unbind a rise/fall tuple of a VHDL generic variable and create rise time and fall time generics of each generic variable that are independent of each other. Then, according to a predetermined correlation policy, the method and system collect delay values in a VHDL standard delay file, sort the delay values, remove duplicate delay values, group the delay values into correlation sets, and output an analysis file. The correlation policy may include collecting all generic variables in a VHDL standard delay file, selecting each generic variable, and performing reductions on the set of delay values associated with each selected generic variable.
    Type: Grant
    Filed: January 2, 2002
    Date of Patent: November 9, 2004
    Assignee: International Business Machines Corporation
    Inventors: Marvin J. Rich, Ashutosh Misra
  • Patent number: 6812541
    Abstract: The semiconductor substrate of the integrated circuit includes at least one dielectrically isolating, vertical buried trench (2) having a height at least five times greater than its width, the trench laterally separating two regions (4, 5), and an epitaxial semiconductor layer (6) coveting the trench. An application is advantageously suited to MOS, CMOS and BiCMOS technologies.
    Type: Grant
    Filed: December 2, 2003
    Date of Patent: November 2, 2004
    Assignee: STMicroelectronics S.A.
    Inventor: Olivier Menut
  • Patent number: 6806748
    Abstract: A sinusoidal signal multiplier circuit produces an output sinusoidal signal substantially without any DC component. This sinusoidal signal multiplier circuit includes a first multiplication cell receiving a first sinusoidal signal at a first input and a second sinusoidal signal at a second input. The first multiplication cell delivers a first output signal. The sinusoidal signal multiplier circuit also includes a second multiplication cell, identical to the first multiplication cell, that receives the second sinusoidal signal at its first input and the first sinusoidal signal at its second input, and delivers a second output signal. The sinusoidal signal multiplier circuit also includes an adder circuit to add the first output signal and the second output signal to provide from the sinusoidal signal multiplier circuit an output signal substantially without any DC component.
    Type: Grant
    Filed: March 19, 2002
    Date of Patent: October 19, 2004
    Assignee: STMicroelectronics S.A.
    Inventor: Luc Garcia
  • Patent number: 6806156
    Abstract: Process for fabricating a transistor comprises producing source and drain extension regions, consisting in forming a gate region on a semiconductor substrate and in implanting dopants into the semiconductor substrate on either side of and at a certain distance from the gate of the transistor. The producing of the source and drain extension regions consists in forming an intermediate layer (Cl) on the sidewalls of the gate (GR) and on the surface of the semiconductor substrate. This intermediate layer is formed from a material that is less dense than silicon dioxide. The implantation of dopants (IMP) is carried out through that part of the intermediate layer that is located on the semiconductor substrate.
    Type: Grant
    Filed: June 4, 2003
    Date of Patent: October 19, 2004
    Assignee: STMicroelectronics S.A.
    Inventors: Damien Lenoble, Isabelle Guilmeau
  • Patent number: 6787869
    Abstract: Optical semiconductor package (10) and process for fabricating an optical semiconductor package, in which an electrical connection support plate has a through-passage (37); a semiconductor component (34), a front face (33) of which has an optical sensor and which is fixed to a rear face of the plate in such a way that its optical sensor is situated opposite the through-passage; electrical connection (38) connects the optical component to the support plate; the component is encapsulated on the rear face of the support plate; a lid (50), which is at least partially transparent, is fixed to a front face of the support plate and covers the through-passage; and external electrical connections (51) are located on an exposed part of the support plate. Furthermore, another semiconductor component (41) may be fixed to the rear face of the support plate (43) and electrically connected, to the latter, this component also being encapsulated (49).
    Type: Grant
    Filed: September 20, 2002
    Date of Patent: September 7, 2004
    Assignee: STMicroelectronics S.A.
    Inventor: Julien Vittu
  • Patent number: 6778019
    Abstract: A biasing device includes closed-loop transconductance slaving circuit, able to slave the time average of the base/emitter or gate/source voltage of the amplifier transistor (Q1) to a reference voltage corresponding to a desired quiescent current for the transistor. Moreover, viewed from the base or gate of the amplifier transistor (Q1), the impedance of the base/emitter or gate/source circuit is small at low frequency, and large with respect to the impedance of the radio frequency source within the radio frequency range of the signal. The device can be incorporated in a mobile terminal, such as a cellular mobile phone.
    Type: Grant
    Filed: December 20, 2002
    Date of Patent: August 17, 2004
    Assignee: STMicroelectronics S.A.
    Inventors: Jean-Charles Grasset, Frederic Bossu
  • Patent number: 6735031
    Abstract: A method for writing timing marks on a rotatable storage medium, such as on a disk in a disk drive, includes the steps of: 1) during a rotation of the disk, detecting the passage of at least a portion of a first timing mark located at a first radius of the disk, and 2) writing a second timing mark at a second radius of the disk, the location of the second timing mark being based at least in part on a stored calculation of a delay from the time of passage of the first timing mark during a rotation of the rotatable storage medium. The location of the second timing mark is calculated based on alternative time intervals between detected timing marks and on various functions of the time intervals.
    Type: Grant
    Filed: January 31, 2001
    Date of Patent: May 11, 2004
    Assignee: Hitachi Global Storage Technologies Netherlands B.V.
    Inventors: Timothy J. Chainer, Mark D. Schultz, Bucknell C. Webb, Edward J. Yarmchuk
  • Patent number: 6734483
    Abstract: A production of a capacitor includes the simultaneous production, in at least part of an intertrack insulating layer (3) associated with a given metallization level, on the one hand, of the two electrodes (50, 70) and of the dielectric layer (60) of the capacitor and, on the other hand, of a conducting trench (41) which laterally extends the lower electrode of the capacitor, is electrically isolated from the upper electrode and has a transverse dimension smaller than the transverse dimension of the capacitor, and the production, in the interlevel insulating layer (8) covering the intertrack insulating layer, of two conducting pads (80, 81) which come into contact with the upper electrode of the capacitor and with the conducting trench, respectively.
    Type: Grant
    Filed: August 17, 2001
    Date of Patent: May 11, 2004
    Assignee: STMicroelectronics S.A.
    Inventors: Yves Morand, Jean-Luc Pelloie
  • Patent number: 6727838
    Abstract: The present invention herein describes a tracking analog-to-digital converter, in particular of the differential input type. In an embodiment thereof the tracking analog-to-digital converter, having a differential analog input including a first analog input and a second analog input, and a digital output at a first number of bits comprising: a back and forth counter having a direction input and an output, with a second number of bits; a digital-to-analog converter having a data input coupled to said output of said converter, a reference input and an output, with a second number of bits; a first comparator having a positive input, a negative input coupled to said output of said digital-to-analog converter and an output coupled to said direction input; characterized in that said reference input is coupled to said first analog input and said positive input of said first comparator is coupled to said second analog input.
    Type: Grant
    Filed: September 25, 2002
    Date of Patent: April 27, 2004
    Assignee: STMicroelectronics S.r.l.
    Inventors: Luca Schillaci, Alessandro Scrivani, Simone Silvestri, Maurizio Nessi
  • Patent number: 6724384
    Abstract: A method in an imaging system organizes and compresses into segments of limited size the image collection needed for the application of image based rendering to walkthroughs of large objects. For views from a limited range of positions only a corresponding limited segment of data needs to be transmitted, decompressed, and processed. A savings is thereby obtained in the startup time and memory required for execution of a walkthrough.
    Type: Grant
    Filed: May 16, 2001
    Date of Patent: April 20, 2004
    Assignee: International Business Machines Corporation
    Inventor: Donald H. Weingarten
  • Patent number: 6725217
    Abstract: A computing system and method explores a knowledge repository by accepting a natural language query from a user, determining a distance between the query and every category in every partitioning of the knowledge repository, and displaying a radial graph (322) of the nearest categories. Further, in response to a user selecting a category, visually displaying matching elements in the category along with its nearest neighbor categories in a scatter plot (324).
    Type: Grant
    Filed: June 20, 2001
    Date of Patent: April 20, 2004
    Assignee: International Business Machines Corporation
    Inventors: Amy W. Chow, Jeffrey T. Kreulen, Justin T. Lessler, Larry L. Proctor, W. Scott Spangler
  • Patent number: 6724660
    Abstract: An electronic device, such as an opto-electronic device and an integrated semiconductor memory device, includes at least one integrated memory point structure including a quantum well semiconductor area buried in the substrate of the structure and disposed under the insulated gate of a transistor. A biasing voltage source is adapted to bias the structure to enable charging or discharging of charges in the quantum well or outside the quantum well.
    Type: Grant
    Filed: December 12, 2001
    Date of Patent: April 20, 2004
    Assignee: STMicroelectronics S.A.
    Inventors: Thomas Skotnicki, Stephane Monfray, Michel Haond
  • Patent number: 6719392
    Abstract: A method finds the color gamut of a source device and a destination device in their device-dependent color spaces, converts each color gamut to a device-independent color space, compares the color gamut of the source device to the color gamut of the destination device in the device-independent color space, and finds an optimized intermediate color range in the device-independent color space. Then, the method maps the colors from the color gamut of the source device in the device-independent color space to the optimized intermediate color range using a first gamut-mapping algorithm, maps the colors inside the optimized intermediate color range to the color gamut of the destination device in the device-independent color using a second gamut-mapping algorithm, and converts the colors in the color gamut of the destination device in the device-independent color space back to the color gamut of the destination device in the device-dependent color space.
    Type: Grant
    Filed: December 20, 2001
    Date of Patent: April 13, 2004
    Assignee: International Business Machines Corporation
    Inventor: Yue Qiao
  • Patent number: 6713876
    Abstract: Optical semiconductor package and process for fabricating an optical semiconductor package, in which an electrical connection support plate (2) has a through-passage (5); a first semiconductor component (4) such as a microprocessor placed behind the support plate and lying opposite the through-passage; electrical connection metal balls (9) inserted into the annular space separating the first component from the support plate; encapsulation mechanism including an encapsulation material (12) lying in the annular space; a second semiconductor component (13), a front face (15) of which has an optical sensor and a rear face of which is fixed to the front face (20) of the first component (4) through the through-passage (5) of the support plate (2); metal electrical connection wires (17) connecting the front face of the second component and the front face of the support plate; a front encapsulation lid (21) which covers the through-passage and the metal wires at some distance and which has at least one transparent pa
    Type: Grant
    Filed: October 1, 2002
    Date of Patent: March 30, 2004
    Assignee: STMicroelectronics S.A.
    Inventors: Julien Vittu, Remi Brechignac
  • Patent number: 6700226
    Abstract: A transistor includes a substrate region (14) of a first type (P) of conductivity in a semiconductor material layer of the same type (P) of conductivity, at least a first contact region (13) of the first type (P+) of conductivity inside the substrate region (14) and adjacent to a first terminal (C) of the transistor, a well (11) of second type (N) of conductivity placed inside the substrate region (14), wherein the well (11) of second type (N) of conductivity includes at least a second contact region (12) of a second type of conductivity (N+) adjacent to a region of a second terminal (B) of the transistor, and a plurality of third contact regions (10) of the first type of conductivity (P+) adjacent to a plurality of regions of a third terminal (E1, . . . , E3) of the transistor interposed each one (10) and other (12) by proper insulating shapes (20).
    Type: Grant
    Filed: December 27, 2001
    Date of Patent: March 2, 2004
    Assignee: STMicroelectronic S.r.l.
    Inventors: Loris Vendrame, Paolo Caprara, Giorgio Oddone, Antonio Barcella