Abstract: A coprocessor (200) is proposed, using a single multiplication circuit (228 and 231) coupled to a computation circuit (240) dedicated to the computation of Y0, with Y0=(X*J0)mod 2k, J0 being defined by the equation ((N*J0)+1)mod 2k=0. The computation of Y0 is done bit by bit, during one half-cycle of a clock signal before the use of each bit. A method is also proposed for the computation of a modular operation using the circuit (240) for the computation of Y0.

Abstract: A circuit architecture and a method for performing a trimming operation directly on an application board, or after the operation of packaging integrated electronic devices. The circuit architecture includes at least one non-volatile memory unit (3) having non-volatile memory elements (5) and a circuit (17, 19) for modifying the state of the memory elements (5), a first multifunctional input pin (8) whereon a sequence (25) of trimming data is received, a second multifunctional input pin (9) whereon a timing signal of the trimming operations is received, and an additional access pin (7) for switching the circuit architecture operation from a normal mode over to a trimming mode.

Abstract: A protection device includes a switching transistor (M11), connected between the gate of the output transistor (TS1) and ground, and a control circuit (CM), connected to the gate of the switching transistor (M11), which are capable of ensuring that the switching transistor (M11) is off when there is no electrostatic discharge at the drain of the output transistor (TS1) and capable of turning the switching transistor (M11) on when there is an electrostatic discharge at the drain of the output transistor (TS1).

Abstract: A communication system (100) includes a network, a first application running on a first Host computer system (First Host) (102) coupled to the network, and a second application running on a second Host computer system (Second Host) (122) coupled to the network. The first application issues an Extended PING command (300) for sending an Extended ECHO message (380) from the First Host (102) into the network and directed to the second application in the Second Host (122). The second application in the Second Host (122), in response to receiving the Extended ECHO message (380), issues an Extended PING command (300) for sending an Extended ECHO reply message (380) into the network and directed to the first application to measure the full loop-back network latency of communicating a message application-to-application across the network.

Abstract: A communication system (100) includes at least one digital signal processor (DSP) and a WAN driver (80) operating on a processor that is electrically coupled to a memory. The WAN driver (80) receives task allocation requests from a host to open/close communication channels that are handled by the at least one DSP. Each task is allocated to one of the at least one DSP according to a total current task processing load for each of the at least one DSP, a maximum processing capability for each of the at least one DSP, and a processing requirement for each task being allocated to the one of the at least one DSP that can handle the additional processing load of the task being allocated.

Abstract: A method and apparatus for indexing and searching content in a hardcopy document utilizes a searching assistant computing device (402) with an index table (420) stored in memory (412). The index table (420) is created in memory by scanning a 2-D barcode from a hardcopy document or alternatively by downloading indexing information from a web page via the Internet (430). A search engine (410) in the searching assistant (402) searches the index table (420) to locate a data element found in the content of the hardcopy document. The indexing information corresponding to the data element is displayed to a user as part of the search results to indicate the location of the data element in the hardcopy document.

Abstract: The integrated circuit comprises a semiconductor substrate SB supporting a memory cell PM of the DRAM type comprising an access transistor T and a storage capacitor TRC. The access transistor is made on the substrate, and the substrate includes a capacitive trench TRC buried beneath the transistor and forming the storage capacitor, the capacitive trench being in contact with one of the source and drain regions of the transistor.

Abstract: A portable electronic device includes a sound system having one or more speakers, each located at an impact point of the electronic device. Each speaker includes a sound chamber and shock absorbing means for protecting the electronic device from a force resulting from an impact between the electronic device and another object.

Abstract: An integrated circuit chip (IC) is equipped with a device for preventing reverse engineering by monitoring light emissions emitted from transistors and such electrically active devices in a circuit located in the IC. The device can be an opaque structure that blocks emissions from being detected external to the IC. Alternatively, the device can reduce light emissions from the transistors to prevent detection of the light emissions external to the IC. The device, in another alternative, can emit extraneous light emissions to hide a pattern of light emissions emitted from the transistors. As a further alternative, the device can add random delay to a signal driving the transistors to randomize the pattern of light emissions emitted from the transistors to prevent detection of a predetermined pattern of light emissions external to the IC.

Abstract: A method and apparatus for reverse engineering an integrated circuit chip (IC chip) (120) utilizes an electrical circuit tester (114) for injecting a triggering signal into the IC chip (120) to exercise a circuit under test. In synchronization thereto, a PICA detector (116) monitors optical emissions from the circuit under test. A spatial data extractor, electrically coupled to the PICA detector, collects space information (124) from patterns of light emissions emitted by the circuit under test, and a timing data extractor, electrically coupled to the electrical circuit tester and to the PICA detector (116), collects time information (126) from the patterns of light emissions emitted by the circuit under test. A database memory (105) includes known data about the circuit under test and also includes at least one reference pattern for comparing a captured light emission pattern thereto to identify at least one circuit element in the circuit under test.

Abstract: An electronic circuit with digital output including an auto-stable assembly of latches (1), a control assembly (2), a blowable assembly (3), a logic gate (4) including a first input connected to a common point (14) between the auto-stable assembly (1) and the blowable assembly (3), and a second input connected to the control input (20) of the electronic circuit. A breaker (5) is controlled by the output of the logic gate (4) and arranged between the auto-stable assembly (1) and ground, and an associated process.

Abstract: A micro-pipeline type asynchronous circuit and a method for detecting and correcting soft error. The asynchronous circuit records in a first recording unit a signal output by a calculation unit and then records in a second recording unit the same signal delayed by at least the duration of the pulse of a soft error. The recorded signals then are compared in a comparer circuit. If they are identical, no soft error has been detected and the output signal is recorded after another delay that is longer than the pulse duration of the soft error, and a request signal is transmitted to a control unit of a next logic stage with a delay twice as long as the pulse duration of a soft error.

Abstract: A transistor manufacturing process includes the formation, on a layer (15) that will form the base of the transistor, of a stack of an SiGe alloy layer (16), a silicon oxide layer (17) and a silicon nitride layer (18), so as to form in this layer, a false emitter (20), to form, in the layer (15) that will form the base, an extrinsic base region (22) and to siliconize the surface of this extrinsic base region, to cover the extrinsic base region (22) and the false emitter (20) with a silicon dioxide layer (24) which is chemically and mechanically polished down to the level of the false emitter (20), to etch the false emitter (20) in order to form a window (25) and to form, in the window (25) and on the silicon dioxide layer (24), a polysilicon emitter (27). This process has particular application to manufacturing heterojunction bipolar transistors.

Abstract: A method for writing timing marks on a rotatable storage medium, such as on a disk in a disk drive, includes the steps of: 1) during a rotation of the disk, detecting the passage of at least a portion of a first timing mark located at a radial trajectory at a first radius of the disk, and 2) during the same rotation of the disk, writing a second timing mark at a second radius of the disk. The second timing mark is located at least one of a) where at least a portion of the second timing mark overlaps at least a portion of the radial trajectory of the first timing mark, and b) where the second timing mark is in close proximity to the radial trajectory of the first timing mark. The second timing mark is written based on different parameters such as a measured time interval, a calculated time interval, and a predetermined delay.

Abstract: An integrated circuit includes an array of memory cells that are selected by rows and read by columns. The columns are first precharged by an internal signal to then read the memory cells. The read is responsive to an edge of a clock signal and the read is of an unknown delay. A multiplexer output provides the internal signal. The multiplexer includes a plurality of inputs electrically connected to delay lines of different delay sizes that receive the edge of the clock signal. A multiplexer control circuit selects a delay line to provide the internal signal as soon as possible after the unknown delay.

Abstract: A gas containing structure includes a film (100), that can be formed into a foldable sheet (802), bag (1200), or liner (1404, 1408, 1504, 1508) for a rigid container such as a box, can, or bottle. The film (100) includes at least one gas containing storage volume, i.e., at least one store (106), that is at least partially contained by the film (100). The at least one store (106) contains a gas including oxygen that is energizably convertible, such as by an ultraviolet radiation energy source (1002, 1004), to sanitizing agent including ozone gas in the at least one store (106). The sanitizing agent can provide at least one of a sanitizing, disinfecting, and sterilizing, application to an object or product (402). The film (100) can be applied by wiping, wrapping, and packaging the object or product (402). The film (100) can be re-used for a subsequent sanitizing application.

Abstract: A column register of an integrated circuit memory, notably in EEPROM technology, is utilized in a method of writing a data word of 2p bits in the memory, where p is a non-zero whole number. The method includes the following steps: 1) erasing all the cells of the word; 2) loading 2q data in 2q high-voltage latches (HV1, HV3, HV5, HV7), and loading 2p-2q other data in the 2p-2q low-voltage latches (LV0, LV2, LV4, LV6); and 3) programming 2q cells of the memory (M0, M2, M4, M6) as a function of the data memorized in the 2q high-voltage latches; as well as repeating 2p-q−1 times the following steps: 4) loading, in the 2q high-voltage latches, of 2q other data that were loaded in the 2q low-voltage latches at step 2); and 5) programming 2q other cells of the memory (M1, M3, M5, M7) as a function of the data memorized in the 2q high-voltage latches.

Abstract: A process and an integrated circuit are intended for obtaining an adjustable electrical resistance, in which a first voltage is applied to an integrated MOS transistor on its source, its gate and its substrate, and a second voltage is applied on its drain, the first and second voltages being able to initiate a breakdown of the MOS transistor by: avalanche of the drain/substrate junction; biasing of the parasitic bipolar transistor of the MOS transistor; irreversible breakdown of the drain/substrate junction; and shorting between the drain and the source.