Abstract: A method for assisting the recall of retail good information in a point of sale (POS) system can include the steps of scanning an identifier associated with a retail good; searching a translation table for retail good information corresponding to the scanned identifier; and, if the retail good information cannot be found in the translation table in the searching step, displaying a list of retail good information previously assigned to the scanned identifier. In a preferred embodiment, the retail good information can be a purchase price corresponding to the retail good.

Abstract: An adapter circuit in power supplies utilizes a selective voltage doubler which approximately doubles an input voltage with a low line connector and does not with a high line connector. The selective voltage doubler is coupled to a switcher, which in turn is coupled to a resonant circuit. The resonant circuit is coupled to a first diode and a second diode and a filter. When a low line connector is used, the input voltage is doubled and a one diode drop is used. When a high line connector is used, the input voltage is not doubled and a two diode drop is used.

Abstract: A component assembly in accordance with the present invention is disclosed. In a first aspect, the assembly includes at least one component and a bracket for holding at least one component. The bracket has a first side, a second side, and formed features for holding at least one component to the first side of the bracket. The assembly includes a wire spring assembly for securing at least one component to the second side of the bracket. In a second aspect, the component assembly comprises a first component and a second component. The component assembly further includes a bracket for holding the first and second components on the first and second sides of the bracket. The first and second sides of the bracket are oppositely disposed to each other. The bracket includes formed features on the first and second sides for retaining the first and second components.

Abstract: A device for attaching at least two pieces of a material is disclosed. The device comprises a first portion, the first portion comprising an opening and a ledge therein and a latching mechanism hingedly coupled to the first portion wherein the latching mechanism is capable of being attachably coupled to the first portion via the ledge. Accordingly, the device in accordance with the present invention is easy to open and close, latches securely, and stays closed during package stress testing.

Abstract: A system for monitoring tamper events in a computer system is disclosed. The computer system is on a network. The system comprises a tamper real time clock (RTC) means which receives at least one tamper event signal from the computer system. The tamper RTC means includes a timer for indicating the time of a tamper event and a management device for receiving the at least one tamper event signal. The management device issues a command to the tamper RTC means to obtain the time of the at least one tamper event. The management device also generates a network packet which includes the time of the tamper event to a system administrator of the network. The present invention in a preferred embodiment is directed to a computer system which has the ability to functionally detect and store the time of a tamper event. A tamper real time clock (RTC) circuit is operatively connected with logic to store the date and time of an event as it occurs.

Abstract: The present invention provides a cross-bar switch which includes a plurality of master bus ports, the master bus ports adapted to receive a plurality of master buses; a plurality of slave bus ports, the slave bus ports adapted to receive a plurality of slave buses; a manner of switching for selectively coupling the plurality of master bus ports to the plurality of slave bus ports; and a manner of configuration for prioritizing access requests by the plurality of master buses to the plurality of slave buses via the switching means. The cross-bar switch of the present invention has the capability of prioritizing requests between multiple parallel high speed buses. In a preferred embodiment, this arbitration is accomplished through Configuration Registers on the cross-bar switch. The Configuration Registers are programmable through the Device Control Register bus, which allows the cross-bar switch to be dynamically programmed and changed by a processor in a larger system.

Abstract: The present invention is directed toward a method, system and computer readable medium (the present invention) for reporting information related to a monitor attached to a computer which includes a system memory. The present invention includes electronically reading the information from the monitor and storing the monitor information in the system memory. The present invention further includes retrieving the monitor information from the system memory and providing the monitor information to a display via a browser. The monitor information comprises electronically readable information including its identity. One aspect of the present invention further includes comparing the monitor information with a corresponding last known information, wherein a mismatch indicates that the monitor has been changed. Another aspect of the present invention further includes copying the monitor information to a radio frequency (RF) enabled memory, wherein the monitor information can be logged utilizing an RF reader device.

Abstract: A system and method for monitoring tamper events in a computer system in accordance with the present invention is disclosed. The system comprises a detector means for detecting at least one tamper event and for providing an indication when the tamper event has occurred for longer than a predetermined time period. The system also includes an adapter means coupled to the detector means for receiving the indication and for disabling the computer system. The present invention is directed to a computer system, which has the ability to functionally determine if a tamper event is authorized and therefore allows the computer to operate after such an event. In a preferred embodiment, the tamper event could be as simple as a toggle switch being activated when the cover of the personal computer is removed.

Abstract: A method and system for processing an event notification generated by a proxy managed object in a management system, where the management system includes at least one manager and at least one agent. The agent includes a proxy agent coordinator, at least one proxy agent containing one or more event forwarding discriminators, and at least one proxy managed object. The method includes the steps of providing a proxy agent identifier in the notification generated by the proxy managed object, comparing the proxy agent identifier in the notification to an identifier stored in the event forwarding discriminator, and processing the notification if the identifier in the notification matches the identifier stored in the event forwarding discriminator.

Abstract: The present invention is directed toward a method, system and computer readable medium (the present invention) for tracking memory modules in a computer system. The present invention includes identifying each of the memory modules based upon identification information added to each of the memory modules by their manufacturer to provide a unique serial number by each of the memory modules; and providing the unique serial number to a display via a browser. The identification information comprises electronically readable information which is preferably stored in an electronically erasable programmable read only memory (EEPROM) and from which the unique serial numbers are generated for identifying the memory modules. One aspect of the present invention further includes comparing the unique serial numbers with corresponding last known serial numbers, wherein a mismatch in the serial numbers indicates that the corresponding memory modules have been replaced.

Abstract: The present invention is directed towards a method and system for retrieving and reporting serial numbers of hard disk drives in a computer system. The method and system include electronically obtaining the serial number of each of the hard disk drives. The method and system also include providing the serial number of each of the hard disk drives to a display via a browser. The method and system additionally include copying the serial number of each of the hard disk drives to a radio frequency (RF) enabled memory, wherein the serial numbers can be logged utilizing an RF reader. The RF reader may be included in an RF gate and/or a hand held device. Computer systems with Radio Frequency Identification (RFID) technology configured in accordance with the present invention enable automated electronic tracking of computer assets such as the hard disk drives as they pass through the RF gate in or out of a portal.

Abstract: Aspects for isolating faults in a redundant power converter are described. An exemplary system aspect includes a first switch at an input of the redundant power converter for protecting the redundant power converter from a high input voltage, and a second switch coupled within the redundant power converter prior to an output capacitor, wherein efficiency of fault isolation is improved.

Abstract: The present invention provides a device and method for securing integrity of a blind autodock electrical connection in a computer system. A method and device according to the present invention for insuring integrity of a blind autodock electrical connection for use with a computer system includes a stationary assembly and a module. The method and device comprises a first electrical connector coupled to the stationary assembly and a second electrical connector coupled to the module. It also includes a connector sensor coupled to the first connector, and a connector sensor receiver coupled to the second connector. The connector sensor is a device including connector sensors which are coupled via a wire.

Abstract: A programmable circuit is used to modify the write enable signal used by static RAMs in cache-based personal computer systems. More specifically, the programmable circuit is used to delay or not delay the trailing edge of the cache write enable (CWE) signals in cache-based personal computer systems thereby enabling the system to accommodate a plurality of microprocessor devices.

Abstract: A translator circuit for providing symmetrical switching delays for use with a power line for a differential amplifier having a first signal line and a complementary second signal line, the translator circuit including: a first voltage clamp coupled to the first signal line and to the power line for limiting a voltage differential between the power line and the first signal line; and a second voltage clamp coupled to the power line and the second signal line for limiting a voltage differential between the power line and the second signal line. The translator circuit provides reduced sensitivity to variations in process parameters, power supply voltages, temperature and manufacturing tolerances. The translator circuit also provides symmetrical tracking between the rise to rise and the fall to fall delays of an emitter coupled logic to complementary metal-oxide semiconductor translator circuit.

Abstract: A system is provided on an Integrated Multiport Repeater (IMR) to monitor the activity of the IMR when the repeater is in minimum mode. Through this system the serial output pin outputs status based upon inputs at two input pin the signal in and the clock signal. In a preferred embodiment there are four different status outputs, partition, loopback/link, Bitrate and SQE/Polarity. This system finds use in low end applications where complex control circuitry is not desired.

Abstract: A gate clamping circuit is disclosed that includes a logic gate and a bias circuit arrangement. Through this clamping circuit the speed of operation of the circuit during both low to high and high-to-low transitions of the output signal are optimized while power consumption is minimized.

Abstract: An output buffer circuit is disclosed that minimizes propagation delay and crowbar current. This circuit receives a data input signal and provides an output signal. This circuit includes a pull-up transistor, a first pull-down transistor, a speed improvement circuit and a crowbar current reduction circuit. The speed improvement circuit comprises an inverter with small propagation delay coupled to a second pull-down transistor which is smaller than the first pull-down transistor. The speed improvement circuit minimizes the propagation delay of the circuit when the data input signals changes from a high logic level to a low logic level by speeding up the initial rate of fall of the output signal due to the fast turning on of the second small pull-down transistor which receives the data input signal quickly through the small-propagation-delay inverter. The crowbar current reduction circuit comprises a first crowbar current reduction transistor which is smaller than the pull-up transistor.

Abstract: An improved circuit topology for implementing level detection and data restoration operations on an input sinusoid. The differential high-frequency level detector and data restoration circuits of the present invention each include a differential input having a pair of circuit nodes for receiving a differential input signal. A slicing offset network is disposed to generate first and second differential signals in response to the differential input signal. The present invention further includes first and second comparators for respectively providing latch set and latch reset signals in response to the first and second offset differential signals. The data restoration circuit of the present invention further includes a latch operative to synthesize a recovered data waveform in accordance with pairs of set and reset signals. Similarly, the inventive level detector includes a latch which utilizes set and reset signals to generate a level detection signal.

Abstract: A system provides for detection of enhanced capabilities of stations on a communications network. A specified pattern of link test pulses are detected and transmitted to provide for the indication of enhanced capabilities. This is particularly useful for determining whether a particular station is in full duplex or half duplex mode without affecting overall network performance.